[1] 肖杰,江建慧,等.一个面向缺陷分析的电路成品率与可靠性关系模型[J].电子学报,2014,42(4):747-755. Xiao Jie,Jiang Jian-hui,et al.A defect analysis-oriented relation model of circuit yield and reliability[J].Acta Electronica Sinica,2014,42(4):747-755.(in Chinese)
[2] Banerjee A,Chatterjee A.Signature driven hierarchical post-manufacture tuning of RF systems for performance and power[J].IEEE Transactions on VLSI Systems, 2015,23(2):342-355.
[3] Radfar M,Singh J.A yield improvement technique in severe process,voltage,and temperature variations and extreme voltage scaling[J].Microelectronics Reliability,2014,54(12):2813-2823.
[4] Mani M,Devgan A,Orshansky M.An efficient algorithm for statistical minimization of total power under timing yield constraints[A].Proceedings of Design Automation Conference[C].California,USA:ACM,2005.309-314.
[5] 李鑫,Janet M Wang,等.工艺随机扰动下非均匀互连线串扰的谱域方法分析[J].电子学报,2009,37(2):398-403. Li Xin,Janet M Wang,et al.Spectral method for analysis of crosstalk of non-uniform RLC interconnects in the presence of process variations[J].Acta Electronica Sinica,2009,37(2):398-403.(in Chinese)
[6] Liu X X,Palma-Rodriguez A A,Rodriguez-Chavez S.Performance bound and yield analysis for analog circuits under process variations[A].Proceedings of The Asia and South Pacific Design Automation Conference[C]. Yokohama,Japan:ACM,2013.761-766.
[7] Wei W E,Li H Y,Han C Y.A flexible TFT circuit yield optimizer considering process variation,aging,and bending effects[J].IEEE/OSA Journal of Display Technology,2014,10(12):1055-1063.
[8] 卜登立,江建慧.基于对偶逻辑的混合极性RM电路极性转换和优化方法[J].电子学报,2015,43(1):79-85. Bu Deng-li,Jiang Jian-hui.Dual logic based polarity conversion and optimization of mixed polarity RM circuits[J].Acta Electronica Sinica,2015,43(1):79-85.(in Chinese)
[9] Srivastava A,Kaviraj C,et al.A novel approach to perform gate-level yield analysis and optimization considering correlated variations in power and performance[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2008,27(2):272-285.
[10] Xie L,Davoodi A.Robust estimation of timing yield with partial statistical information on process variations[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2008,27(12) 2264-2276.
[11] Orshansky M,Bandyopadhyay A.Fast statistical timing analysis handling arbitrary delay correlations[A].Proceedings of Design Automation Conference[C].California,USA:ACM,2004.337-342.
[12] Rao R,Srivastava A,et al.Statistical analysis of subthreshold leakage current for VLSI circuits[J].IEEE Transactions on Very Large Scale Integration Systems,2004,12(2):131-139.
[13] Mani M,Devgan A,et al.A statistical algorithm for power-and timing-limited parametric yield optimization of larger integrated circuits[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2007,26(10):1790-1802.
[14] Hwang E J,Kim W,Kim Y H.Timing yield slack for timing yield-constrained optimization and its application to statistical leakage minimization[J].IEEE Transactions on Very Large Scale Integration Systems,2013,21(10):1783-1796.
[15] Orshansky M.Statistical minimization of total power under timing yield constraints[A].Proceedings of IEEE International Conference on Integrated Circuit Design & Technology[C].Grenoble,France:IEEE,2006.1-4.
[16] Mande S S,Chandorkar A N,Iwai H.Computationally efficient methodology for statistical characterization and yield estimation due to inter-and intra-die process variations[A].Proceedings of Asia Symposium on Quality Electronic Design[C].Penang,Malaysia:IEEE,2013.287-294.
[17] Sheng Y,Xu K,Wang D,Chen R.Performance analysis of FET microwave devices by use of extended spectral-element time-domain method[J].International Journal of Electronics,2013,100(5):699-717.
[18] Sun J,Huang Y,et al.Chebyshev affine arithmetic based parametric yield prediction under limited descriptions of uncertainty[A].Proceedings of The Asia and South Pacific Design Automation Conference[C].Seoul,Korea:ACM,2008.531-536.
[19] Zhu W,Wu Z.The stochastic ordering of mean-preserving transformations and its applications[J].European Journal of Operational Research,2014,239(3):802-809.
[20] Stolfi J,Figueiredo L H.Self-validated numerical methods and applications[A].Proceedings of Brazilian Math.Colloq.Monograph[C].Netherlands:Academic Press,1997.15-20.
[21] Williamson R C,Downs T.Probabilistic arithmetic I:numerical methods for calculating convolutions and dependency bounds[J].International Journal of Approximate Reasoning,1990,(4):89-158.
[22] Tiwary S K,Tiwary P K,Rutenbar R A.Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration[A].Proceedings of Design Automation Conference[C].California,USA:ACM,2006.31-36. |