基于工艺参数扰动的IC参数成品率多目标优化算法

doi:10.3969/j.issn.0372-2112.2016.12.021

电子学报 ›› 2016, Vol. 44 ›› Issue (12): 2960-2966.DOI: 10.3969/j.issn.0372-2112.2016.12.021

基于工艺参数扰动的IC参数成品率多目标优化算法

李鑫^1,2, 孙晋³, 肖甫², 田江山³

1. 江苏省安全生产科学研究院科技研发中心, 江苏南京 210042;
2. 南京邮电大学江苏省无线传感网高技术研究重点实验室, 江苏南京 210013;
3. 南京理工大学计算机科学与工程学院, 江苏南京 210094

收稿日期:2015-05-11 修回日期:2015-07-01 出版日期:2016-12-25
- 作者简介:
- 李鑫,男,1983年2月出生于江苏省徐州市.2009年毕业于南京理工大学计算机学院.现为江苏省安全生产科学研究院高级工程师,从事VLSI计算机辅助设计与芯片可靠性估计及优化方面的研究工作.E-mail:lin65002@hotmail.com;孙晋,男,1983年5月出生于江苏省淮安市.2011年毕业于亚利桑那大学电子与计算机工程系.现为南京理工大学计算机科学与工程学院副教授.从事集成芯片鲁棒性设计与多核片上网络低功耗设计方面的研究工作.E-mail:sunj@njust.edu.cn

A Multi-objective Optimization Framework for Robust IC Parametric Yield Predication Under Process Variations

LI Xin^1,2, SUN Jin³, XIAO Fu², TIAN Jiang-shan³

1. Technology Innovation Center, Jiangsu Academy of Safety Science and Technology, Nanjing, Jiangsu 210042, China;
2. Jiangsu High Technology Research Key Laboratory for Wireless Sensor Networks, Nanjing University of Posts and Telecommunications, Nanjing, Jiangsu 210013, China;
3. School of Computer Science and Engineering, Nanjing University of Science and Technology, Nanjing, Jiangsu 210094, China

Received:2015-05-11 Revised:2015-07-01 Online:2016-12-25 Published:2016-12-25

摘要/Abstract

摘要：

在芯片制造工艺中，参数扰动影响了集成电路（Integrated Circuit，IC）成品率，使不同参数成品率间存在着此消彼长的相互制约关系，而目前IC参数成品率优化算法却主要局限于单一优化目标问题.本文提出一种基于工艺参数扰动的参数成品率多目标优化算法.该算法针对漏电功耗成品率及芯片时延成品率，首先构建具有随机相关性的漏电功耗及芯片时延统计模型；随后根据其相互制约特性建立基于切比雪夫仿射理论的参数成品率多目标优化模型；最后利用自适应加权求和得到分布均匀的帕雷托优化解.实验结果表明，该算法对于具有不同测试单元的实验电路均可求得大约30个分布均匀的帕雷托优化解，不仅能够有效权衡多个优化目标间的相互制约关系，还可以使传统加权求和优化方法在帕雷托曲线变化率较小之处得到优化解.

关键词: 可制造性设计, 参数成品率, 统计建模, 多目标优化, 帕累托最优

Abstract:

Process variations lead to a significant degradation of IC parametric yield,and they also tend to cause a negative correlation between different parametric yields.However,previous yield optimization works are limited to deal with single objective problem.To deal with the above-mentioned limitation,this paper proposes a multi-objective optimization framework for co-optimization of power and timing yields under process variations.The proposed method starts with establishing explicit statistical models for power and timing metrics respectively.Then considering the negative correlation between the metrics,we employ Chebyshev affine arithmetic to formulate a multi-objective optimization model,optimize power and timing yields simultaneously by adaptive weighted sum method,and provide a well-distributed set of Pareto-optimal solutions.Experimental results demonstrate that the proposed method explores about 30 well-distributed solutions for each benchmark circuit with different test units.In addition,it can not only balance the restricted correlation between multiple optimization objectives,but make the traditional weighted sum method to get optimal solutions on the Pareto curve where change rate is small.

Key words: design for manufacturability, parametric yield, statistical modeling, multi-objective optimization, Pareto optimality

中图分类号:

TN47

李鑫, 孙晋, 肖甫, 田江山. 基于工艺参数扰动的IC参数成品率多目标优化算法[J]. 电子学报, 2016, 44(12): 2960-2966.

LI Xin, SUN Jin, XIAO Fu, TIAN Jiang-shan. A Multi-objective Optimization Framework for Robust IC Parametric Yield Predication Under Process Variations[J]. Acta Electronica Sinica, 2016, 44(12): 2960-2966.

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基于工艺参数扰动的IC参数成品率多目标优化算法

A Multi-objective Optimization Framework for Robust IC Parametric Yield Predication Under Process Variations

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