改进型高速高精度CORDIC算法及其在DDFS中的应用

doi:10.3969/j.issn.0372-2112.2017.02.025

电子学报 ›› 2017, Vol. 45 ›› Issue (2): 446-451.DOI: 10.3969/j.issn.0372-2112.2017.02.025

改进型高速高精度CORDIC算法及其在DDFS中的应用

史方显¹, 曾立¹, 陈昱¹, 王淼¹, 占丰²

1. 北京航空航天大学宇航学院, 北京 100191;
2. 山东航天电子技术研究所, 山东烟台 264000

收稿日期:2015-10-13 修回日期:2016-04-11 出版日期:2017-02-25
- 通讯作者:
- 史方显
- 作者简介:
- 曾立,男,1976年8月出生于湖南邵阳.清华大学博士,北京航空航天大学副教授,研究方向为为空间环境仪器科学与工程.E-mail:09123@buaa.edu.cn
- 基金资助:
- 国家自然科学基金 (No.41274190，No.41074130，No.41327802）

Direct Digital Frequency Synthesizer Based on an Improved High Speed & High Precision CORDIC Algorithm

SHI Fang-xian¹, ZENG Li¹, CHEN Yu¹, WANG Miao¹, ZHAN Feng²

1. School of Astronautics, Beihang University, Beijing 100191, China;
2. Shandong Institute of Aerospace Electronics Technology, Yantai, Shandong 264000, China

Received:2015-10-13 Revised:2016-04-11 Online:2017-02-25 Published:2017-02-25

摘要/Abstract

摘要：

提出了一种新的选择迭代式高速高精度CORDIC（COrdinate Rotation Digital Computer）算法.基于表驱动法缩小目标旋转角度，通过改进的基本角度选择方法旁路不必要的迭代；并以移位和减法实现幅度校正，减小硬件资源消耗.设定角度误差小于10^-5rad时，迭代次数减小至7次以下.在DDFS（Direct Digital Frequency Synthesizer）的应用中，利用区间压缩技术在Xilinx的FPGA中实现20位定点小数电路设计.仿真及实测结果表明，该算法幅度误差小于2×10^-5，输出延时不大于43.5ns，同时硬件资源消耗不增加.

关键词: 坐标旋转数字计算机, 直接数字频率合成器, 表驱动, 现场可编程门阵列

Abstract:

A novel optional-iteration high speed and high precision CORDIC algorithm is proposed in this paper.First the rotation is conducted with a corresponding angle based on table-driven method.Then the algorithm bypasses unnecessary iterations using a new basic angle choosing technique.And the correction is achieved by shift and subtraction to reduce hardware consumption.Calculation and simulation indicate that the new algorithm can reduce the iteration number to less than 7 when the phase error is smaller than 10^-5rad.In the application of DDFS,20 fractional binary bits design is implemented in Xilinx FPGA with range reduction method.This design can reduce amplitude error to smaller than 2×10^-5 for sine and cosine,cut the output delay down to 43.5ns in circuit test,and no hardware consumption increase.

Key words: CORDIC(COrdinate rotation digital computer), DDFS(direct digital frequency synthesizer), table-driven, FPGA(field programmable gate array)

中图分类号:

TN431.2

史方显, 曾立, 陈昱, 王淼, 占丰. 改进型高速高精度CORDIC算法及其在DDFS中的应用[J]. 电子学报, 2017, 45(2): 446-451.

SHI Fang-xian, ZENG Li, CHEN Yu, WANG Miao, ZHAN Feng. Direct Digital Frequency Synthesizer Based on an Improved High Speed & High Precision CORDIC Algorithm[J]. Acta Electronica Sinica, 2017, 45(2): 446-451.

参考文献

[1] Tierney J,Rader C M,Gold B.A digital frequency synthesizer[J].IEEE Transactions on Audio and Electroacoustics,1971,19(1):48-57.
[2] Yang W,Hao M.A direct digital frequency synthesizer based on CORDIC algorithm implemented with FPGA[A].Proceedings of the 5th International Conference on ASIC[C].Beijing,China:IEEE,2003.2:832-835.
[3] Han W,Yousi Z,Xiaokang L.A parallel double-step CORDIC algorithm for digital down converter[A].2009 7th Annual Communication Networks and Services Research Conference (CNSR)[C].Moncton,BC,Canada:IEEE,2009.257-261.
[4] Volder J E.The CORDIC trigonometric computing technique[J].IRE Transactions on Electronic Computers,1959,Ec-8(3):330-334.
[5] 祁艳杰,刘章发.基于Parallel_-CORDIC的高精度高速度直接数字频率合成器的FPGA实现[J].电子学报,2014,42(7):1392-1397. QI Yan-jie,LIU Zhang-fa.FPGA implementation of high speed and high precision direct digital frequency synthesizer based on parallel-CORDIC[J].Acta Electronica Sinica,2014,42(7):1392-1397.(in Chinese)
[6] Xin R,Zhang X,Li H,et al.An area optimized direct digital frequency synthesizer based on improved hybrid CORDIC algorithm[A].3rd International Workshop on Signal Design and Its Applications in Communications[C].Chengdu,China:IEEE,2007.243-246.
[7] Shukla R,Ray K C.Low latency hybrid CORDIC algorithm[J].IEEE Transactions on Computers,2014,63(12):3066-3078.
[8] Chuang T P,Huang C C,Hsiao S F.Design of a CORDIC-based SIN/COS intellectual property (IP) using predictable sign bits[A].Proceedings of the 27th European Solid-State Circuits Conference[C].Villach,Austria:IEEE,2001.277-280.
[9] Han L,Ko S B.High-speed parallel decimal multiplication with redundant internal encodings[J].IEEE Transactions on Computers,2013,62(5):956-968.
[10] Fei Yetai.Error Theory and Data Processing[M].Beijing:Higher Education Press,2010.66-74.(in Chinese)
[11] Hu Y H.The quantization effects of the CORDIC algorithm[J].IEEE Transactions on Signal Processing,1992,40(4):834-844.
[12] Maharatna K,Banerjee S,Grass E,et al.Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture[J].IEEE Transactions on Circuits and Systems for Video Technology,2005,15(11):1463-1474.

[1]	田春生, 陈雷, 王源, 王硕, 周婧, 张瑶伟, 庞永江, 周冲, 马筱婧, 杜忠, 薛钰. 面向FPGA的布局与布线技术研究综述[J]. 电子学报, 2022, 50(5): 1243-1254.
[2]	罗阳锦, 张升伟, 陆浩. 高光谱微波辐射计宽带高速数字系统设计[J]. 电子学报, 2021, 49(2): 380-386.
[3]	曹保锋, 郑毅, 李鹏, 张雪芹, 李欣, 李小强, 胡淼. 微弱电磁脉冲信号低失真度实时检测的FPGA实现[J]. 电子学报, 2019, 47(8): 1797-1802.
[4]	闵富红, 金秋森. 双忆阻Shinriki振荡器的超级多稳态和反单调性分析[J]. 电子学报, 2019, 47(11): 2263-2270.
[5]	王今雨, 伍卫国, 秦朝楠, 赵东方, 聂世强. UPRFloor:一种动态可重构FPGA建模方法与布局策略[J]. 电子学报, 2018, 46(12): 2862-2869.
[6]	李冰, 周岑军, 陈帅, 吉建华. 用于SRAM PUFs的伪随机数发生器的FPGA实现[J]. 电子学报, 2017, 45(9): 2106-2112.
[7]	吴珊, 周学功, 王伶俐. 基于SRAM型FPGA单粒子效应的故障传播模型[J]. 电子学报, 2017, 45(8): 1976-1984.
[8]	张朝柱, 韩吉南, 燕慧智. 高速高精度固定角度旋转CORDIC算法的设计与实现[J]. 电子学报, 2016, 44(2): 485-490.
[9]	李艳, 张东晓, 于芳. RTL综合中FPGA片上RAM工艺映射[J]. 电子学报, 2016, 44(11): 2660-2667.
[10]	周舟, 付文亮, 嵩天, 刘庆云. 一种基于并行Bloom Filter的高速URL查找算法[J]. 电子学报, 2015, 43(9): 1833-1840.
[11]	刘书勇, 吴艳霞, 张博为, 张国印, 戴葵. 基于可重构计算系统的矩阵三角化分解硬件并行结构研究[J]. 电子学报, 2015, 43(8): 1642-1650.
[12]	张晓帆, 李广军. 基于低硬件复杂度、高速CORDIC的SVD模块设计与实现[J]. 电子学报, 2015, 43(4): 738-742.
[13]	陈志辉;章淳;王颖;王伶俐. 一种FPGA抗辐射工艺映射方法研究[J]. 电子学报, 2011, 39(11): 2507-2512.
[14]	杨阳;王永纲;陈巍;王双;张丽君;黄大骏;章涛;韩正甫. 相位编码量子密钥分发系统的电子学设计[J]. 电子学报, 2011, 39(11): 2604-2609.
[15]	谢丁;邵赟;来金梅;王健;陈利光;王元;俞建德. 现代层次化可编程逻辑器件软件系统FDE2009[J]. 电子学报, 2010, 38(5): 1136-1140.

改进型高速高精度CORDIC算法及其在DDFS中的应用

Direct Digital Frequency Synthesizer Based on an Improved High Speed & High Precision CORDIC Algorithm

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics