[1] Santanu Chattopadhyay.Techniques for NoC design and test[A].Vishwani D.Agrawal.2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems[C].Mumbai:IEEE,2014.1-6.
[2] Wang W,Li R F,Fang F,Chen T,Ren F J,Liu J.Design and realization of 3D NoC multicast router base on multicast rotational routing arithmetic[A].Liu X P.IEEE International Conference on Computing,Communication and Networking Technologies (ICCCNT) [C].Hefei:IEEE,2014.1-6.
[3] Bibhas Ghoshal,Indranil Sengupta.A distributed BIST scheme for NoC-based memory cores[A].Eugenio Villar.2013 16th Euromicro Conference on Digital System Design[C].Los Alamitos:IEEE,2013.567-574.
[4] Michael L Bushnell,Vishwani D.Agrawal.超大规模集成电路测试数字存储器核混合信号系统[M].蒋安平,冯建华,王新安,等,译.北京:电子工业出版社,2005.
[5] IEEE Std.1500-2005.IEEE Standard Testability Method for Embedded Core-based Integrated Circuits[S].
[6] 王伟,李欣,陈田,刘军,方芳,吴玺.基于扫描链平衡的3D SoC测试优化方法[J].电子测量与仪器学报,2013,26(7):586-590 WANG Wei,LI Xin,CHEN Tian,LIU Jun,FANG Fang,WU Xi.3D SoC test optimization method based on balance of scan chain[J].Journal of Electronic Measurement and Instrument,2013,26(7):586-590.(in Chinese)
[7] ZHAO Xiong-bo,JIANG Peng-long,LIU Liang-liang.Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard,electronic packaging technology (ICEPT)[A].Aldo Di Carlo.2014 15th International Conference on[C].Chengdu:IEEE,2014.1108-1111.
[8] Ali G,Hussin F A,Ali N B Z,et al.Enhancement in IEEE 1500 standard for at-speed functional testing[A].Vahid Sohani.Intelligent and Advanced Systems (ICIAS),2014 5th International Conference on[C].Kuala Lumpur:IEEE,2014.1-5.
[9] Raik J,Ubar R,Govind V.Test configurations for diagnosing faulty links in NoC switches[A].R Segers Test Symposium,2007 ETS'07 12th IEEE European[C].Freiburg:IEEE,2007.29-34.
[10] Caselli N,Strano A,Ludovici D,et al.Cooperative built-in self-testing and self-diagnosis of NoC bisynchronous channels[A].Shigeaki Tsunoyama.Embedded Multicore Socs (MCSoC),2012 IEEE 6th International Symposium on.IEEE[C].Aizu-Wakamatsu:IEEE,2012.159-166.
[11] 欧阳一鸣,贺超,梁华国.NoC 架构下异构 IP 核的并行测试方法[J].电子学报,2013,41(12):2391-2396. OUYANG Yi-ming,HE Chao,LIANG Hua-guo,HUANG Zheng-feng,XIE Tao.Concurrent testing for heterogeneous-cores in network-on-chips[J].Acta Electronica Sinica,2013,41(12):2391-2396.(in Chinese)
[12] Manna K,Khaitan P,Chattopadhyay S,et al.Particle swarm optimization based technique for network-on-chip testing[A].John Walz.Emerging Applications of Information Technology (EAIT),2012 Third International Conference on[C].Kolkata:IEEE,2012:66-69.
[13] Alexandre M Amory,Eduardo Briao,érika Cota Marcelo Lubaszewski,Fernando G Moraes.A scalable test strategy for network-on-chip routers[A].ITC 2005[C].Austin,TX:IEEE,2005.1-9.
[14] Tran X T,Thonnart Y,Durupt J,et al.A design-for-test implementation of an asynchronous network-on-chip architecture and its associated test pattern generation and application[A].Alex Yakovlev.NoCS 2008.Second ACM/IEEE International Symposium on[C].Newcastle upon Tyne:IEEE,2008.149-158.
[15] 覃晓莹,郑湘南,王政集,粟涛.多模式多时钟域芯片的物理设计方法[J].中山大学学报(自然科学版),2015,54(3):14-18. QIN Xiaoying,ZHENG Xiangnan,WANG Zhengji,SU Tao.Physical design method of multi-mode and multi-clock domain chips[J].Acta Scientiarum Naturalium Universitatis Sunyatseni,2015,54(3):14-18.(in Chinese)
[16] 刘军,吴玺,裴颂伟,王伟,陈田.基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法[J].电子学报,2015,43(3):454-459. LIU Jun,WU Xi,PEI Song-wei,WANG Wei,CHEN Tian.Wrapper scan chains optimization based on span and virtual layers for three dimensional cores[J].Acta Electronica Sinica,2015,43(3):454-459.(in Chinese)
[17] Higgins M,MacNamee C,Mullane B.Design and implementation challenges for adoption of the IEEE 1500 standard[J].IET Computers & Digital Techniques,2010,4(1):38-49.
[18] ITC'02,ITC'02 SoC Test Benchmarks[S].
[19] Becker D U.Efficient Microarchitecture for Network-on-Chip Routers[M].California,USA:Stanford Univer-sity,2012. |