电子学报 ›› 2017, Vol. 45 ›› Issue (4): 937-943.DOI: 10.3969/j.issn.0372-2112.2017.04.024

• 学术论文 • 上一篇    下一篇

基于流体系结构的高效能分组密码处理器研究

王寿成, 严迎建, 徐进辉   

  1. 解放军信息工程大学, 河南郑州 450001
  • 收稿日期:2016-04-18 修回日期:2016-10-19 出版日期:2017-04-25
    • 通讯作者:
    • 王寿成
    • 作者简介:
    • 严迎建 男,1973年生于河南扶沟.教授、硕士生导师.主要从事芯片安全防护、专用芯片设计和密码芯片能量攻击等方面的研究工作.
    • 基金资助:
    • 国家自然科学基金 (No.61404175)

Research of High-Efficient Block Cipher Processor Based on Stream Architecture

WANG Shou-cheng, YAN Ying-jian, XU Jin-hui   

  1. PLA Information Engineering University, Zhengzhou, Henan 450001, China
  • Received:2016-04-18 Revised:2016-10-19 Online:2017-04-25 Published:2017-04-25

摘要:

针对现有密码处理器存在的问题,借鉴流处理器架构,提出了高效能的可重构分组密码流处理器架构.该架构采用层次化设计思想,通过分块式本地寄存器组的数据组织方式和共享拼接使用运算单元机制,实现了软件流水和硬件流水的协同工作,能够挖掘分组内和分组间的指令级并行性并提高功能单元的利用率.在65nm CMOS工艺下对架构进行了综合仿真,并经过了大量算法映射.实验结果证明,该架构在CBC和ECB加密模式下均具有良好的加密性能.与其他密码处理器相比,该架构具有小面积、高效能的特点.

关键词: 分组密码, 流处理器, 可重构, 软件流水, 面积能效比

Abstract:

To solve the existing problem of the cipher processor,high-efficiency reconfigurable block cipher processor based on stream architecture was proposed.Through the efficient data organization and flexible cipher computing units,the processor that adopts the design conception of hierarchy achieves the cooperation of software and hardware pipeline,develops instruction level parallelism in a block and among multiple blocks and improves the utilization rate of functional units.The processor was simulated and synthesized in 65nm CMOS process.The mapping results of typical block cipher algorithms show that it has high encryption performance both in CBC and ECB mode.Compared with other cryptographic processors,this processor has the advantage of small-area and high-efficiency.

Key words: block cipher, stream processor, reconfigurable, software pipeline, area efficiency

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