[1] Estrin G,Bussell B,Turn R,Bibb J.Parallel processing in a restructurable computer system[J].IEEE Transactions Oil Electronic Computers,1963,12(6):747-755.
[2] 张朝昆,崔勇,唐翯祎,等.软件定义网络(SDN)研究进展[J].软件学报,2015,26(1):62-81. Zhang Chaokun,Cui Yong,Tang He-yi,et al.State-of-the-art survey on software-defined networking(SDN)[J].Journal of Software,2015,26(1):62-81.(in Chinese)
[3] Nunes BAA,Mendonca M,Nguyen XN,Obraczka K,Turletti T.A survey of software-defined networking:Past,present,and future of programmable networks[J].IEEE Communications Surveys and Tutorials,2014,16(3):1617-1634.
[4] Software-Defined networking research group (SDNRG)[EB/OL].http://irtf.org/sdnrg,2013.
[5] 兰巨龙,程东年,胡宇翔.可重构信息通信基础网络体系研究[J].通信学报,2014,35(1):128-139. LAN Ju-long,CHENG Dong-nian,HU Yu-xiang.Research on reconfigurable information communication basal network architecture[J].Journal on Communications,2014,35(1):128-139.(in Chinese)
[6] 兰巨龙,邢池强,胡宇翔,等.可重构技术与未来网络体系架构[J].电信科学,2013,29(8):16-23. Lan Julong,Xing Chiqiang,Hu Yuxiang,et al.Reconfiguration technology and future network architecture[J].Telecommunications Science,2013,29(8):16-23.(in Chinese)
[7] Elbirt A J.Reconfigurable computing for symmetric-key algorithms[D].Massachusetts,USA:Electrical and Computer Engineering Department,University of Massachusetts Lowell,2002.
[8] AJ Elbirt.Instruction-level distributed processing for symmetric-key cryptography[A].In:International Parallel and Distributed Processing Symposium (IPDPS'03)[C].Nice,France 2003.78.
[9] Fronte D,Perez A,Payrat E.Celator:A multi-algorithm cryptographic co-processor[A].In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig'08)[C].IEEE Computer Society,Los Alamitos,CA,2008.438-443.
[10] Ravi S,Raghunathan A,Potlapally N,et al.System design methodologies for a wireless security processing platform[A].Proceedings of the 39th annual Design Automation Conference[C].New Orleans,Louisiana,USA:ACM,2002.777-782.
[11] Hauser J R,Wawrzynek J.Garp:A MIPS processor with a reconfigurable coprocessor[A].Proceedings of Field-Programmable Custom Computing Machines[C].Los Alamitos,CA,USA:IEEE,1997.12-21.
[12] Mirsky E,DeHon A.MATRIX:a reconfigurable computing architecture with configurable instruction distribution and deployable resources[A].IEEE Symposium on FPGAs for Custom Computing Machines[C].Napa,CA,USA:IEEE,1996.157-166.
[13] Marshall,Alan,et al.A reconfigurable arithmetic array for multimedia applications[A].Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays[C].New York,USA:ACM,1999.135-143.
[14] Liang C,Huang X.SmartCell:An energy efficient coarse-grained reconfigurable architecture for stream-based applications[J].EURASIP Journal on Embedded Systems,2009(1):1-15.
[15] Hartenstein R,Herz M,Hoffmann T.Mapping applications onto reconfigurable kressArray[A].Proceedings of 9th International Workshop on Field Programmable Logic and Applications[C].Berlin,German:Springer LNCS 1673,1999.385-390.
[16] 姜晶菲.可重构密码处理结构的研究与设计[D].长沙:国防科技大学,博士论文,2007.
[17] 曲英杰.可重组密码逻辑的设计原理[D].北京:北京科技大学.2002.
[18] 杨晓辉.面向分组密码处理的可重构设计技术研究[D].郑州:中国人民解放军信息工程大学.2007.
[19] Wang Y,Liu L,Yin S,et al.On-chip memory hierarchy in one coarse-grained reconfigurable architecture to compress memory space and to reduce reconfiguration time and data-reference time[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2014,22(5):983-994.
[20] Bossuet L,Grand M,Gaspar L,et al.Architectures of flexible symmetric key crypto engines-a survey:From hardware coprocessor to multi-crypto-processor system on chip[J].ACM Computing Surveys (CSUR),2013,45(4):41.
[21] Granado-Criado J M,Vega-Rodríguez M A,Sánchez-Pérez J M,et al.A new methodology to implement the AES algorithm using partial and dynamic reconfiguration[J].INTEGRATION,the VLSI journal,2010,43(1):72-80.
[22] Francisco Fons,Mariano Fons,Enrique Cantó,Mariano López.Deployment of run-time reconfigurable hardware coprocessors into compute-intensive embedded applications[J].Journal of Signal Processing Systems,2012,66(2):191-222.
[23] Pérez O,Berviller Y,Tanougast C,et al.The use of runtime reconfiguration on FPGA circuits to Increase ihe performance of the AES algorithm implementation[J].Journal of Universal Computer Science,2007,13(3):349-362.
[24] Ismaili Z E A A,Moussa A.Self-partial and dynamic reconfiguration implementation for AES using FPGA[J].International Journal of Computer Science Issues,2009(2):33-40.
[25] Hori Y,Satoh A,Sakane H,et al.Bitstream encryption and authentication using AES-GCM in dynamically reconfigurable systems[A].International Workshop on Security[C].Berlin,German:Springer,2008.261-278.
[26] Le Masle A,Luk W,Eldredge J,et al.Parametric encryption hardware design[A].International Symposium on Applied Reconfigurable Computing[C].Berlin,German:Springer,2010.68-79.
[27] Öksüzoglu E,Savas E.Parametric,secure and compact implementation of RSA on FPGA[A].2008 International Conference on Reconfigurable Computing and FPGAs[C].Los Alamitos,California,USA:IEEE,2008.391-396.
[28] Eisenbarth T,Güneysu T,Paar C,et al.Reconfigurable trusted computing in hardware[A].Proceedings of the 2007 ACM workshop on Scalable trusted computing[C].New York,USA:ACM,2007.15-20.
[29] Glas B,Klimm A,Sander O,et al.A system architecture for reconfigurable trusted platforms[A].Proceedings of the conference on Design,automation and test in Europe[C].New York,USA:ACM,2008.541-544.
[30] Malipatlolla S,Feller T,Shoufan A,et al.A novel architecture for a secure update of cryptographic engines on trusted platform module[A].2011 International Conference on Field-Programmable Technology (FPT)[C].Piscataway,NJ,USA:IEEE,2011.1-6.
[31] Conte A,Anquetil L P.Design for application protocol stack framework[A].IEEE International Conference on Communications[C].New Orleans:IEEE,2000.565-570.
[32] Stefan B.Ken M,Brian W.Application-compliant networking on embedded systems[A].Proc of 5th IEEE International Workshop on Networked Appliances Manchester[C].Piscataway,NJ,USA:IEEE,2002.53-58.
[33] Moon J T,Kim J S,Kim J B,et al.A hardware implementation of distributed network protocol[J].Computer Standards and Interfaces,2005,27(3):221-232.
[34] 蔡衍文,陈天洲,吴朝晖.面向通信设备的网络协议构件化[J].计算机应用究,2004,21(12):253-256. Cai Yan-wen,Chen Tian-zhou,Wu Zhao-hui.Component-based Network Protocols on Communication Device[J].Application Research of computers,2014,21(12):253-256.(in Chinese)
[35] Casado R,Bermudez A,Duato J,et al.A protocol for deadlock-free dynamic reconfiguration in high-speed local area networks[J].IEEE Trans on Parallel and Distributed Systems,2001,12(2):115-132.
[36] Casado R,Bermudez A,Quiles F J,et al.Influence of network size and load on the performance of reconfiguration protocols[A].IEEE International Symposium on Network Computing and Applications[C].Cambridge,IEEE,2001.46-57.
[37] Casado R,Bermudez A,Duato J,et al.Performance evaluation of dynamic reconfiguration in high-speed local area networks[A].Proceedings of 6th International Symposium on High-Performance Computer Architecture[C].Toulouse,IEEE,2000.85-96.
[38] Jedhe G S,Ramamoorthy A,Varghese K.A scalable high throughput firewall in FPGA[A].16th International Symposium on Field-Programmable Custom Computing Machines[C].Los Alamitos,CA,USA:IEEE,2008.43-52.
[39] Lee T K,Yusuf S,Luk W,et al.Compiling policy descriptions into reconfigurable firewall processors[A].11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines,2003[C].Los Alamitos,CA,USA:IEEE,2003.39-48.
[40] Kai Zhang,Xiaoming Ding,Ke Xiong,Shuo Dai.RSS:A reconfigurable security system designed on NetFPGA and virtex5-LX110T[A].1st European NetFPGA Developers Workshop[C].Oxford,UK:University of Cambridge,2010.
[41] Tan T H,Ooi C Y,Hau Y W,et al.Remote dynamically reconfigurable platform using NetFPGA[A].2014 IEEE International Symposium on Circuits and Systems (ISCAS)[C].Piscataway,NJ,USA:IEEE,2014.1239-1242.
[42] Tan T H,Ooi C Y,Marsono M N.rrBox:A remote dynamically reconfigurable network processing middlebox[A].201525th International Conference on Field Programmable Logic and Applications (FPL)[C].London,UK:Imperial College,2015.1-4.
[43] Bossuet L,Fischer V,Gaspar L,et al.Disposable configuration of remotely reconfigurable systems[J].Microprocessors and Microsystems,2015,39(6):382-392.
[44] Qi Y,Fong J,Jiang W,et al.Multi-dimensional packet classification on FPGA:100 Gbps and beyond[A].2010 International Conference on Field-Programmable Technology (FPT)[C].Piscataway,NJ,USA:IEEE press,2010.241-248.
[45] Salman A,Rogawski M,Kaps J P.Efficient hardware accelerator for IPSec based on partial reconfiguration on Xilinx FPGAs[A].2011 International Conference on Reconfigurable Computing and FPGAs[C].Piscataway,NJ,USA:IEEE,2011.242-248.
[46] Wang H,Bai G,Chen H.A gbps IPSec SSL security processor design and implementation in an FPGA prototyping platform[J].Journal of Signal Processing Systems,2010,58(3):311-324.
[47] Isobe T,Tsutsumi S,Seto K,et al.10 Gbps implementation of TLS/SSL accelerator on FPGA[A].201018th International Workshop on Quality of Service (IWQoS)[C].Piscataway,NJ,USA:IEEE,2010.1-6.
[48] Hamilton M,Marnane W P.Implementation of a secure TLS coprocessor on an FPGA[J].Microprocessors and Microsystems,2016,40(2):167-180.
[49] Paul R,Chakrabarti A,Ghosh R.Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm[J].Microprocessors and Microsystems,2016,40:124-136.
[50] Chaves R,Kuzmanov G,Sousa L.On-the-fly attestation of reconfigurable hardware[A].2008 International Conference on Field Programmable Logic and Applications,FPL 2008[C].Heidelberg,Germany:Kirchhoff Institute for Physics,IEEE,2008.71-76.
[51] Kastner R,Huffmire T.Threats and challenges in reconfigurable hardware security[R].California Univ San Diego La Jolla,Dept of Computer Science and Engineering,July 2008.
[52] Drimer S,Kuhn M G.A protocol for secure remote updates of FPGA configurations[A].International Workshop on Applied Reconfigurable Computing[C].Berlin German:Springer,2009.50-61.
[53] Huffmire T,Brotherton B,Callegari N,et al.Designing secure systems on reconfigurable hardware[J].ACM Transactions on Design Automation of Electronic Systems (TODAES),2008,13(3): 44.
[54] Saar Drimer.Volatile FPGA design security-a survey[EB/OL].http://www.cl.cam.ac.uk/sd410,2008.1-42.
[55] Drzevitzky S,Kastens U,Platzner M.Proof-carrying hardware:Towards runtime verification of reconfigurable modules[A].2009 International Conference on Reconfigurable Computing and FPGAs[C].Piscataway,NJ:IEEE,2009.189-194.
[56] Silva V D,Kroening D,Weissenbacher G.A survey of automated techniques for formal software verification[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2008,27(7):1165-1178. |