[1] COMPTON K,HAUCK S. Reconfigurable computing:a survey of systems and software[J]. ACM Computing Surveys,2002,34(2):171-210.
[2] WU L,WEAVER C,AUSTINT. CryptoManiac:A fast flexible architecture for secure communication[J]. Computer Architecture:Proceedings Annual International Symposium 2001,29(2):110-119.
[3] 黄伟.面向云计算的性能与功耗可配置安全终端技术研究[D].上海:复旦大学,2011.
[4] BOSSUET L,GRAND M,GASPAR L,et al. Architectures of flexible symmetric key crypto engines-a survey:from hardware coprocessor to multi-crypto-processor system on chip[J]. ACM Computing Surveys,2013,45(4):115-123.
[5] GRAND M,BOSSUET L,GAL B L,et al. Design and implementation of a multi-core crypto-processor for software defined radios[A]. Andreas Koch. Reconfigurable Computing:Architectures,Tools and Applications[C]. Berlin:Springer Berlin Heidelberg,2011. 29-40.
[6] 杨晓辉,戴紫彬,张永福. 可重构分组密码处理结构模型研究与设计[J]. 计算机研究与发展,2009,46(6):962-967. YANG Xiao-hui, DAI Zi-bin,ZHANG Yong-fu.Research and design of reconfigurable computing targeted at block cipher processing[J]. Journal of Computer Research and Development, 2009, 46(6):962-967. (in Chinese)
[7] 陈韬,罗兴国,李校南,等. 一种基于流处理框架的可重构分簇式分组密码处理结构模型[J]. 电子与信息学报,2014,12(12):3027-3034. CHEN Tao,LUO Xing-guo,LI Xiao-nan,et al.An architecture of stream based reconfigurable clustered block cipher processing array[J]. Journal of Electronics & Information Technology,36(12):3027-3034.(in Chinese)
[8] SAYILAR G,CHIOU D. Cryptoraptor:high throughput reconfigurable cryptographic processor[A].Marculescu D. The IEEE/ACM International Conference on.Computer-Aided Design[C]. San Jose,CA:IEEE,2014.155-161.
[9] 孟涛,戴紫彬. 分组密码处理器的可重构分簇式架构[J]. 电子与信息学报,2009,2(2):453-456. MENG Tao DAI Zi-bin.Reconfigurable clustered architecture of block cipher processor[J]. Journal of Electronics & Information Technology,2009,31(2):453-456.(in Chinese)
[10] SAYILAR G. Cryptoraptor:High Throughput Reconfigurable Cryptographic Processor for Symmetric Key Encryption and Cryptographic Hash Functions[D]. Texas:The University of Texas at Austin,2014.
[11] 夏辉,贾智平,张峰,李新,陈仁海,EdwinH.-M.Sha. AES专用指令处理器的研究与实现[J]. 计算机研究与发展,2011,48(08):1554-1562. XIA Hui,JIA Zhiping,ZHANG Feng,et al.The research and application of a specific instruction processor for AES[J].Journal of Computer Research and Development,2011,48(08):1554-1562. (in Chinese)
[12] LI R,Sun B,LI C,et al. Differential fault analysis on sms4 using a single fault[J]. Information Processing Letters,2011,111(4):156-163.
[13] BIHAM E,DUNKELMAN O,KELLER N,et al. New attacks on IDEA with at least 6 rounds[J]. Journal of Cryptology,2015,28(2):209-239.
[14] DUNKELMAN O,KELLER N,SHAMIR A. A practical-time related-key attack on the KASUMI cryptosystem used in GSM and 3G telephone[J]. Journal of Cryptology,2014,27(4):824-849.
[15] 李曼曼,陈少真. 对ARIA算法中间相遇攻击的改进[J]. 通信学报,2015,36(3):277-282. LI Man-man,CHEN Shao-zhen.Improved meet-in-the-middle attack on ARIA cipher[J].Journal on Communications,2015,36(3):277-282.(in Chinese)
[16] SUGIO N,AONO H,SEKINO K,et al. A new higher order differential of Camellia[A]. Kasai K. The International Symposium on Information Theory and Its Applications (ISITA)[C]. Melbourne Australia:IEEE,2014.478-482.
[17] BUCHTY R. CRYPTONITE-A Programmable Crypto Processor Architecture for High-bandwidth Applications[D]. Munchen:Institut fur Informatik der Technischen Universitat Munchen,2002.
[18] THEODOROPOULOS D,PAPAEFSTATHIOU I,PNEVMATIKATOS D.N. CCproc:An efficient cryptographic coprocessor[A]. Torres L. The 16th IFIP/IEEE International Conference on Very Large Scale Integration[C]. Montpellier France:IEEE,2008.160-163.
[19] FRONTE D,PEREZ A,PAYRAT E. Celator:A multi-algorithm cryptographic co-processor[A]. Cumplido R. The International Conference on Reconfigurable Computing and FPGAs[C]. Cancun,Mexico:IEEE,2008:438-443.
[20] 郭岩松,刘雷波. 一种面向分组密码的粗粒度可重构阵列及AES算法映射[J]. 微电子学与计算机,2015,32(09):1-5. GUO Yan-song,LIU Lei-bo.A block cipher oriented coarse-grained reconfigurable array and AES algorithm mapping[J].Microelectronics & Computer,2015,32(09):1-5.(in Chinese)
[21] LIU B. BAAS B M. Parallel AES encryption engines for many-core processor arrays[J].IEEE Transactions on Computers,2013,62(3):536-547. |