电子学报 ›› 2017, Vol. 45 ›› Issue (6): 1382-1388.DOI: 10.3969/j.issn.0372-2112.2017.06.015

• 学术论文 • 上一篇    下一篇

一种低功耗双重测试数据压缩方案

陈田1,2, 易鑫1,2, 王伟1,2, 刘军1,2, 梁华国1,3, 任福继2,4   

  1. 1. 合肥工业大学计算机与信息学院, 安徽合肥 230009;
    2. 合肥工业大学情感计算与先进智能机器安徽省重点实验室, 安徽合肥 230009;
    3. 合肥工业大学电子科学与应用物理学院, 安徽合肥 230009;
    4. 德岛大学, 日本德岛770-8506
  • 收稿日期:2015-11-05 修回日期:2016-03-07 出版日期:2017-06-25 发布日期:2017-06-25
  • 通讯作者: 陈田
  • 作者简介:易鑫 男,1991年生于贵州遵义.现为合肥工业大学计算机与信息学院硕士研究生.主要研究方向为VLSI/SoC低功耗测试和可测性设计.E-mail:yixin@mail.hfut.edu.cn;王伟 男,1979年生于安徽合肥.现为合肥工业大学计算机与信息学院副教授、硕士生导师.主要研究方向为VLSI/SoC低功耗测试和可测性设计.E-mail:wangwei_hfut@hfut.edu.cn
  • 基金资助:

    国家自然科学基金(No.61204046,No.61474035,No.61306049);国家自然科学基金重点项目(No.61432004);高等学校博士学科点专项科研新教师基金(No.2013JYXJ0650)

Low Power Multistage Test Data Compression Scheme

CHEN Tian1,2, YI Xin1,2, WANG Wei1,2, LIU Jun1,2, LIANG Hua-guo1,3, REN Fu-ji2,4   

  1. 1. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;
    2. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei, Anhui 230009, China;
    3. School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei, Anhui 230009, China;
    4. The University of Tokushima, Tokushima 770-8506, Japan
  • Received:2015-11-05 Revised:2016-03-07 Online:2017-06-25 Published:2017-06-25

摘要:

随着集成电路制造工艺的发展,VLSI(Very Large Scale Integrated)电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗.

关键词: 测试向量相容, 低功耗测试, 测试数据压缩, 双重压缩

Abstract:

With the development of the integrated circuit(IC) manufacturing technology,very large scale integrated(VLSI) circuits test is faced with the problems of over large test data volume and high test power consumption.This paper presents a low-power multistage test data compression scheme to address these two problems.Firstly,the proposed scheme preprocesses the original test set with the input reduction technology so as to reduce the volume of specified bits;secondly,the scheme compresses test patterns shifted in multi-scan chains according to their compatibilities and uses shorter code to demonstrate compatible test patterns,namely the first stage of compression;thirdly,the low power X-filling is conducted:X-filling for capture power reduction is first conducted for the unspecified bits to keep the capture power under the given threshold and then the remaining unspecified bits are filled for shift power reduction;finally,the proposed scheme further compresses test patterns using modified run-length coding.Experimental results for ISCAS89 benchmark circuits demonstrate that,compared with golomb,FDR,EFDR,9C,BM code,etc.,the proposed scheme achieves better compression rate while reducing both the capture power and the shift power.

Key words: test vector compatible, low power test, test data compression, multistage compression

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