沟道宽度对65nm金属氧化物半导体器件负偏压温度不稳定性的影响研究

doi:10.3969/j.issn.0372-2112.2018.05.016

电子学报 ›› 2018, Vol. 46 ›› Issue (5): 1128-1132.DOI: 10.3969/j.issn.0372-2112.2018.05.016

沟道宽度对65nm金属氧化物半导体器件负偏压温度不稳定性的影响研究

崔江维¹, 郑齐文¹, 余德昭², 周航^1,2, 苏丹丹^1,2, 马腾^1,2, 魏莹^1,3, 余学峰¹, 郭旗¹

1. 中国科学院特殊环境功能材料与器件重点实验室, 新疆电子信息材料与器件重点实验室, 中国科学院新疆理化技术研究所, 乌鲁木齐, 新疆 830011;
2. 中国科学院大学,北京 100049

收稿日期:2017-04-26 修回日期:2017-08-23 出版日期:2018-05-25
- 通讯作者:
- 郑齐文
- 作者简介:
- 崔江维 女,河北石家庄人。微电子学与固体电子学博士,现为中国科学院新疆理化技术研究所副研究员.主要从事半导体材料和器件的辐射效应和可靠性研究.E-mail:cuijw@ms.xjb.ac.cn
- 基金资助:
- 国家自然科学基金 (No.11475255，No.11505282）; 中国科学院西部之光项目 (No.2015-XBQN-B-15）

Effect of Channel Width on NBTI in 65nm PMOSFET

CUI Jiang-wei¹, ZHENG Qi-wen¹, YU De-zhao², ZHOU Hang^1,2, SU Dan-dan^1,2, MA Teng^1,2, WEI Ying^1,3, YU Xue-feng¹, GUO Qi¹

1. The Key Laboratory of Functional Materials and Devices for Special Environments, Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, Urumqi, Xinjiang 830011, China;
2. University of Chinese Academy of Science, Beijing 100049, China

Received:2017-04-26 Revised:2017-08-23 Online:2018-05-25 Published:2018-05-25
- Corresponding author:
- ZHENG Qi-wen
- Supported by:
- National Natural Science Foundation of China (No.11475255, No.11505282); Program of West Light Foundation of The Chinese Academy of Sciences (No.2015-XBQN-B-15)

摘要/Abstract

摘要： 随着MOS器件尺寸缩小，可靠性效应成为限制器件寿命的突出问题.PMOS晶体管的负偏压温度不稳定性（NBTI）是其中关键问题之一.NBTI效应与器件几何机构密切相关.本文对不同宽长比的65nm工艺PMOSFET晶体管开展了NBTI试验研究.获得了NBTI效应引起的参数退化与器件结构的依赖关系，试验结果表明65nm PMOSFET的NBTI损伤随沟道宽度减小而增大.通过缺陷电荷分析和仿真的方法，从NBTI缺陷产生来源和位置的角度，揭示了产生该结果的原因.指出浅槽隔离（STI）区域的电场和缺陷电荷是导致该现象的主要原因.研究结果为器件可靠性设计提供了参考.

关键词: 65nm, 负偏压温度不稳定性, 沟道宽度

Abstract: As the size of MOS device shrinks,the reliability effect becomes a prominent problem that limits the lifetime of the device.Negative bias temperature instability (NBTI) of PMOSFET is one of the key issues.NBTI degradation is closely related to the device geometry.In this paper,we investigate the NBTI effect of 65nm PMOSFET.By experiment,we obtain the dependency of NBTI degradation on device structure,and find that the NBTI damage of 65nm PMOSFET in this paper increases with the decrease of the channel width.By the method of defect charge analysis and TCAD simulation,we reveal the reason on the experimental result from the point of view of defect generation source and position.It is pointed out that the electric field and the defect charge in the shallow trench isolation (STI) region are the main causes of this phenomenon.The results provide a reference for device reliability design.

Key words: 65nm, NBTI, channel width

中图分类号:

TN386.1

崔江维, 郑齐文, 余德昭, 等. 沟道宽度对65nm金属氧化物半导体器件负偏压温度不稳定性的影响研究[J]. 电子学报, 2018, 46(5): 1128-1132.

CUI Jiang-wei, ZHENG Qi-wen, YU De-zhao, et al. Effect of Channel Width on NBTI in 65nm PMOSFET[J]. Acta Electronica Sinica, 2018, 46(5): 1128-1132.

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沟道宽度对65nm金属氧化物半导体器件负偏压温度不稳定性的影响研究

Effect of Channel Width on NBTI in 65nm PMOSFET

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