电子学报 ›› 2018, Vol. 46 ›› Issue (10): 2534-2538.DOI: 10.3969/j.issn.0372-2112.2018.10.030

• 科研通信 • 上一篇    下一篇

软硬件协同设计的SEU故障注入技术研究

王晶1, 荣金叶2, 周继芹3, 于航3, 申娇3, 张伟功1,3   

  1. 1. 首都师范大学信息工程学院, 北京 100048;
    2. 北京微电子技术研究所, 北京 100076;
    3. 首都师范大学电子系统可靠性技术北京市重点实验室, 北京 100048
  • 收稿日期:2016-12-20 修回日期:2017-08-14 出版日期:2018-10-25 发布日期:2018-10-25
  • 通讯作者: 张伟功
  • 作者简介:王晶,女,1982年生于黑龙江哈尔滨,首都师范大学副教授.研究兴趣包括计算机系统结构、容错计算、高能效计算.E-mail:jwang@cnu.eud.cn;荣金叶,女,1983年生于河北邯郸,硕士,工程师.研究方向为嵌入式系统设计.E-mail:yezi_0306@163.com
  • 基金资助:
    国防973项目;国家自然科学基金(No.61772350,No.61472260,No.61741211);北京市高水平教师队伍建设计划(No.CIT&TCD201704082,No.CIT&TCD20170322);体系结构国家重点实验室开放课题(No.CARCH201607);北京市科技新星计划(No.XX2018081);深圳市科技计划项目(No.JCYJ20150529164656096,No.JCYJ20170302153955969)

The Research on Software-Hardware Co-designed SEU Fault-Injection Technology

WANG Jing1, RONG Jin-ye2, ZHOU Ji-qin3, YU Hang3, SHEN Jiao3, ZHANG Wei-gong1,3   

  1. 1. College of Information Engineering, Capital Normal University, Beijing 100048, China;
    2. Beijing Microelectronics Technology Institute, Beijing 100076, China;
    3. Beijing Key Laboratory of Electronic System Reliability Technology, Capital Normal University, Beijing 100048, China
  • Received:2016-12-20 Revised:2017-08-14 Online:2018-10-25 Published:2018-10-25

摘要: 针对现有容错计算机故障注入方法缺乏对空间环境中频发的单粒子故障模型的支持,本文提出了一种利用背板技术的软硬件协同仿真与故障注入技术,分别针对寄存器部件和存储器部件的特性,设计了多位错误的单粒子故障模型,在寄存器传输级实现了通过软件生成故障并注入到硬件设计中的软硬件协同故障注入方案,避免了在硬件设计中修改代码生成故障破坏系统完整性的问题.基于Leon2内核的故障注入实验表明,本文设计的平台为处理器容错设计提供了一个自动化、非侵入、低开销的故障注入和可靠性评估方案.

关键词: 容错, 故障注入, 软硬件协同, 单粒子翻转, 微处理器, 寄存器传输级

Abstract: The existing real-world or simulated fault injection methods cannot meet the requirements of reliability verification of nanoscale microprocessors for space applications,since they may introduce problems such as high cost,poor flexibility,poor observability,and low accuracy.This paper proposes a hardware/software cooperated fault injection scheme based on backplane,the time and positions of fault are generated in software,and injected into hardware design at register transfer level.Further,a multi-bit fault model focuses on radiation-induced soft error is proposed for register and memory.Experimental results show that the proposed software and hardware co-designed fault injection platform provides a high automation,randomicity and non-intrusion reliability evaluation method for fault-tolerant processor design.

Key words: fault-tolerant, fault injection, software-hardware co-design, single event upset, microprocessor, RTL

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