针对现有容错计算机故障注入方法缺乏对空间环境中频发的单粒子故障模型的支持，本文提出了一种利用背板技术的软硬件协同仿真与故障注入技术，分别针对寄存器部件和存储器部件的特性，设计了多位错误的单粒子故障模型，在寄存器传输级实现了通过软件生成故障并注入到硬件设计中的软硬件协同故障注入方案，避免了在硬件设计中修改代码生成故障破坏系统完整性的问题.基于Leon2内核的故障注入实验表明，本文设计的平台为处理器容错设计提供了一个自动化、非侵入、低开销的故障注入和可靠性评估方案.
Abstract
The existing real-world or simulated fault injection methods cannot meet the requirements of reliability verification of nanoscale microprocessors for space applications, since they may introduce problems such as high cost, poor flexibility, poor observability, and low accuracy. This paper proposes a hardware/software cooperated fault injection scheme based on backplane, the time and positions of fault are generated in software, and injected into hardware design at register transfer level. Further, a multi-bit fault model focuses on radiation-induced soft error is proposed for register and memory. Experimental results show that the proposed software and hardware co-designed fault injection platform provides a high automation, randomicity and non-intrusion reliability evaluation method for fault-tolerant processor design.
关键词
容错 /
故障注入 /
软硬件协同 /
单粒子翻转 /
微处理器 /
寄存器传输级
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Key words
fault-tolerant /
fault injection /
software-hardware co-design /
single event upset /
microprocessor /
RTL
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中图分类号：
TP302.8
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参考文献
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脚注
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基金
国防973项目; 国家自然科学基金 (No.61772350，No.61472260，No.61741211）; 北京市高水平教师队伍建设计划 (No.CIT&TCD201704082，No.CIT&TCD20170322）; 体系结构国家重点实验室开放课题 (No.CARCH201607）; 北京市科技新星计划 (No.XX2018081）; 深圳市科技计划项目 (No.JCYJ20150529164656096，No.JCYJ20170302153955969）
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