一种提高芯片良率的时序电路缓冲器插入算法

doi:10.3969/j.issn.0372-2112.2018.12.020

电子学报 ›› 2018, Vol. 46 ›› Issue (12): 2964-2969.DOI: 10.3969/j.issn.0372-2112.2018.12.020

一种提高芯片良率的时序电路缓冲器插入算法

戢小亮¹, 佟星元¹, 吴睿振², 杜鸣³

1. 西安邮电大学电子工程学院, 陕西西安 710121;
2. 西安电子科技大学博士后流动站, 陕西西安 710071;
3. 西安电子科技大学微电子学院, 陕西西安 710071

收稿日期:2017-11-21 修回日期:2018-04-13 出版日期:2018-12-25
- 作者简介:
- 戢小亮 女,1981年生,讲师,研究方向:数字集成电路设计,信号与信息处理.E-mail:jiliangzi@126.com;佟星元 男,1984年生,博士/博士后,副教授,研究方向:集成电路设计.E-mail:mayxt@126.com
- 基金资助:
- 国家自然科学基金 (No.61674122）; 新一代宽带无线移动通信网科技重大专项 (No.2016ZX03001003-006）; 陕西省创新人才推进计划项目 (No.2017KJXX-46）

A Sequential Circuit Buffer Insertion Algorithm for Yield Improvement of Chips

JI Xiao-liang¹, TONG Xing-yuan¹, WU Rui-zhen², DU Ming³

1.School of Electronic Engineering, Xi'an University of Posts & Telecommunications, Xi'an, Shaanxi 710121, China;(;
2.Postdoctoral Station of Xidian University, Xi'an, Shaanxi 710071, China;(;
3.School of Microelectronics, Xidian University, Xi'an, Shaanxi 710071, China

Received:2017-11-21 Revised:2018-04-13 Online:2018-12-25 Published:2018-12-25

摘要/Abstract

摘要： 针对集成电路工艺参数波动影响芯片良率的问题，提出一种提高芯片良率的时序电路缓冲器插入算法.该算法通过蒙特卡罗仿真模拟流片后的芯片，确定时序电路中可插入缓冲器的最佳位置，在保证良率的前提下，降低了面积及成本损耗.算法经过ISCAS89的基准电路和TAU2013的电路进行仿真验证，结果表明插入缓冲器的数量小于等于触发器数量的1%，良率提高高达35.98%.

关键词: 工艺参数波动, 芯片良率, 缓冲器

Abstract: Chip Process variations cause yield degradation after manufacturing. To improve yield, the sequential circuit buffer insertion algorithm for yield improvement of chips is proposed. The locations of buffers are determined by sequential circuit simulating chips after manufacturing based on Monte Carlo simulations. The proposed method not only maintains a good yield improvement, but also reduces area cost. By using ISCAS89 benchmarks and TAU 2013 circuits, the simulation results show that the number of inserted buffers is no larger than 1% of the number of flip-flops in the circuits, and the yield is improved up to 35.98%.

Key words: process variations, yield, buffer

中图分类号:

TP391.41

戢小亮, 佟星元, 吴睿振, 杜鸣. 一种提高芯片良率的时序电路缓冲器插入算法[J]. 电子学报, 2018, 46(12): 2964-2969.

JI Xiao-liang, TONG Xing-yuan, WU Rui-zhen, DU Ming. A Sequential Circuit Buffer Insertion Algorithm for Yield Improvement of Chips[J]. Acta Electronica Sinica, 2018, 46(12): 2964-2969.

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一种提高芯片良率的时序电路缓冲器插入算法

A Sequential Circuit Buffer Insertion Algorithm for Yield Improvement of Chips

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