电子学报 ›› 2019, Vol. 47 ›› Issue (8): 1717-1723.DOI: 10.3969/j.issn.0372-2112.2019.08.015

• 学术论文 • 上一篇    下一篇

针对级联型IIR滤波器群延时的均衡优化技术

佟星元, 贺璐璐, 杜慧敏, 董嗣万   

  1. 西安邮电大学电子工程学院, 陕西西安 710121
  • 收稿日期:2018-10-18 修回日期:2019-04-08 出版日期:2019-08-25 发布日期:2019-08-25
  • 通讯作者: 佟星元
  • 作者简介:贺璐璐 女,1992年出生于陕西省,西安邮电大学硕士,主要研究方向为数字滤波器设计优化.E-mail:919183451@qq.com;杜慧敏 女,1966年出生,西安邮电大学电子工程学院教授,主要研究方向为数字集成电路设计、计算机体系结构等.E-mail:duhuimin0529@126.com;董嗣万 男,1988年出生,西安邮电大学电子工程学院讲师,主要研究方向为模拟集成电路设计.E-mail:dsiwan@163.com
  • 基金资助:
    国家自然科学基金(No.61674122);陕西省创新人才推进计划项目(No.2017KJXX-46);陕西省留学回国人员科技活动优秀资助项目(No.2017005);陕西省高层次人才特殊支持计划项目

Equalization Based Optimization Technique for Group Delay of Cascaded IIR Filter

TONG Xing-yuan, HE Lu-lu, DU Hui-min, DONG Si-wan   

  1. 1. School of Electronics Engineering, Xi'an University of Posts and Telecommunications, Xi'an, Shaanxi 710121, China
  • Received:2018-10-18 Revised:2019-04-08 Online:2019-08-25 Published:2019-08-25

摘要: 为了减小由非恒定群延时所引起的滤波器的输出信号失真,本文提出一种适用于级联型无限长脉冲响应数字滤波器的群延时均衡优化方法.通过在级联型ⅡR数字滤波器每一级的输出插入全通均衡器,减小群延时在通带范围内的变化,进而减小滤波器的输出信号失真.对于本文提出的群延时优化方法,当采用1阶和2阶均衡器进行电路优化时,在0~100Hz的通带范围内,分别将群延时的变化量减小了28.19%和49.93%.基于0.18μm CMOS标准单元库进行逻辑综合与版图设计,最终得到整个滤波电路IP核版图的面积为0.1747mm2.相比于已有文献方法,本文方法在群延时优化上效果显著,电路实现上功耗和面积较小,非常适合片上系统应用.

关键词: 数字滤波器, 无限长脉冲响应, 级联型, 群延时, 全通均衡器

Abstract: In order to reduce the output distortion that caused by the non-constant group delay of digital filter,an equalization based optimization technique is proposed,in this paper,for decreasing the variation of group delay in cascaded infinite-impulse response digital filter.By inserting all-pass equalizer behind each stage of the cascaded ⅡR digital filter,the variation of group delay within the passband range can be reduced,and the output distortion of the digital filter can also be decreased.For the group delay optimization method proposed in this paper,when the 1st and 2nd order equalizers are used for circuit optimization,the variation of group delay is reduced by 28.19% and 49.93% respectively in the passband range of 0~100Hz.Based on the 0.18μm CMOS standard cell library for logic synthesis and layout design,the area of the entire filter circuit IP core layout is 0.1747mm2.Compared with the existing literature methods,this method has a significant effect on group delay optimization,and the power consumption and area are small in circuit implementation,which is very suitable for system-on-chip applications.

Key words: digital filter, IIR(Infinite Impulse Response), cascaded, group delay, all-pass equalizer

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