高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究

doi:10.3969/j.issn.0372-2112.2019.11.012

电子学报 ›› 2019, Vol. 47 ›› Issue (11): 2317-2322.DOI: 10.3969/j.issn.0372-2112.2019.11.012

高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究

李浩^1,2, 任建伟¹, 杜寰¹

1. 中国科学院微电子研究所, 北京 100029;
2. 中国科学院大学, 北京 100049

收稿日期:2018-09-14 修回日期:2018-12-10 出版日期:2019-11-25
- 作者简介:
- 李浩男,1991年生于重庆合川.现为中国科学院微电子研究所在读博士研究生.主要研究方向为射频功率LDMOS器件鲁棒性与PA设计.E-mail:lihao1@ime.ac.cn;任建伟 女,1987年生于陕西咸阳.现为中国科学院微电子研究所助理研究员.主要研究方向为射频功率放大器电路及内匹配研究.E-mail:renjianwei@ime.ac.cn;杜寰男,1963年生于湖南常德.现为中国科学院微电子研究所研究员.主要研究方向为射频功率LDMOS器件与微驱动显示.E-mail:duhuan@ime.ac.cn

The Electrical Mechanism Study of High-Ruggedness N-Channel RF-LDMOS Under TLP Stress

LI Hao^1,2, REN Jian-wei¹, DU Huan¹

1. Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China;
2. University of Chinese Academy of Sciences, Beijing 100049, China

Received:2018-09-14 Revised:2018-12-10 Online:2019-11-25 Published:2019-11-25

摘要/Abstract

摘要： 提高射频功率器件的鲁棒性有利于增强器件的抗静电放电能力和抗失配能力.为了直观地了解器件内部发生的电学过程，本文研究了高鲁棒性N型沟道RF-LDMOS（Radio Frequency Lateral Diffusion MOS）在TLP（Transmission Line Pulse）应力下的电学机理.利用0.18μm BCD（Bipolar/CMOS/DMOS）先进制程，实现了特定尺寸器件的设计与流片.通过实测与仿真的对比，发现静电放电失效的随机性、芯片内部的热效应是导致仿真和实测差异的非理想因素.通过对TLP仿真的各阶段重要节点的分析，证明了源极下方的P型埋层有利于提高空穴电流的泄放能力，从而提高RF-LDMOS的鲁棒性.

关键词: 射频功率器件, LDMOS, 芯片设计, BCD制程, TLP, 碰撞电离, P型埋层

Abstract: Improving the ruggedness of radio frequency power device is beneficial to enhance the ability of withstanding electro-static discharge (ESD) and output mis-match. To understand the electrical process happened in device intuitively, the electrical mechanism of state-of-art high-ruggedness N-channel RF-LDMOS (Radio Frequency Lateral Diffusion MOS), under TLP (Transmission Line Pulse) stress,has been studied. RF-LDMOS FETs with different gate widths had been manufactured using advanced 0.18μm BCD (Bipolar/CMOS/DMOS) process. It is found that the different failure points of simulation and measurement are coming from the random failure of ESD stress and thermal problems. The simulation results of different nodes under TLP stress proved that the P buried layer under source area plays an important role in holes flowing, and improves the ruggedness of RF-LDMOS.

Key words: RF power device, LDMOS, chip design, BCD process, TLP, impact ionization, P buried layer

中图分类号:

TN386.4

李浩, 任建伟, 杜寰. 高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究[J]. 电子学报, 2019, 47(11): 2317-2322.

LI Hao, REN Jian-wei, DU Huan . The Electrical Mechanism Study of High-Ruggedness N-Channel RF-LDMOS Under TLP Stress[J]. Acta Electronica Sinica, 2019, 47(11): 2317-2322.

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高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究

The Electrical Mechanism Study of High-Ruggedness N-Channel RF-LDMOS Under TLP Stress

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