抗电磁干扰低电压CMOS放大器设计

doi:10.3969/j.issn.0372-2112.2015.09.028

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电子学报 ›› 2015, Vol. 43 ›› Issue (9) : 1870-1874. DOI: 10.3969/j.issn.0372-2112.2015.09.028

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抗电磁干扰低电压CMOS放大器设计

白会新, 李洪革, 谢树果, 苏东林

作者信息 +

Design of Low-Voltage CMOS Amplifier with High Electromagnetic Interference Immunity

BAI Hui-xin, LI Hong-ge, XIE Shu-guo, SU Dong-lin

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摘要

基于CMOS体驱动,提出低电压放大器抗电磁干扰结构.电路采用部分正反馈结构提高体驱动输入级的等效输入跨导,通过输入电压降结构改善体驱动结构的直流非线性,采用双输入级结构保证放大器良好的交流特性,同时,对称拓扑结构保证了电路的高度对称性,实现了对称的转换速率.该设计采用电源电压为1V的0.35μm标准CMOS工艺实现.对该放大器的抗电磁干扰特性进行理论分析与仿真验证,并同传统体驱动放大器相比较.实验结果表明:该结构的电压失调小于50mV,10kHz频点的输出功率谱密度相比传统结构降低33dBm.

Abstract

Based on CMOS bulk-driven structure,a low-voltage amplifier with high electromagnetic interference (EMI) immunity is proposed.In the circuit,a partial positive feedback enhances its effective transconductance and an input voltage-drop structure modifies its direct current (DC) nonlinearity.For the overall amplifier,a dual input-stage guarantees its good alternating current (AC) feature,and a symmetrical topology ensures its symmetry and symmetrical slew rate (SR).The amplifier was implemented in a 0.35 μ m standard CMOS process using 1V power supply.Theoretical analysis and simulation results for EMI robustness are presented and compared with the classical bulk-driven amplifier.The results show that the offset voltage of the proposed amplifier is less than 50mV and the output power spectrum density (PSD) at 10kHz is 33dBm lower than that of the classical structure.

导出引用

白会新, 李洪革, 谢树果, 苏东林. 抗电磁干扰低电压CMOS放大器设计[J]. 电子学报, 2015, 43(9): 1870-1874. https://doi.org/10.3969/j.issn.0372-2112.2015.09.028

BAI Hui-xin, LI Hong-ge, XIE Shu-guo, SU Dong-lin. Design of Low-Voltage CMOS Amplifier with High Electromagnetic Interference Immunity[J]. Acta Electronica Sinica, 2015, 43(9): 1870-1874. https://doi.org/10.3969/j.issn.0372-2112.2015.09.028

中图分类号： TN432

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