[1] Zang W, Gordon-Ross A.A survey on cache tuning from a power/energy perspective[J].ACM Computing Surveys (CSUR), 2013, 45(3):32.
[2] ZHENG Z, Zhiying W, Li S.Region-based way-partitioning on L1 data cache for low power[J].IEICE Transactions on Information and Systems, 2013, 96(11):2466-2469.
[3] Xiangyun Z, Lianfeng Z, Dong B.Research on the low power design method for the embedded multi-core processor[A].2013 Fourth International Conference on Digital Manufacturing and Automation (ICDMA) [C].IEEE, 2013.1141-1144.
[4] Inoue K, Ishihara T, Murakami K.Way-predicting set-associative cache for high performance and low energy consumption[A].Proceedings of the 1999 International Symposium on Low Power Electronics and Design [C].ACM, 1999.273-275.
[5] Chen H C.Design of a low-power way-predicting cache using valid-bit pre-decision strategy[J].Journal of the Chinese Institute of Engineers, 2008, 31(5):805-814.
[6] Ye J, Ding H, Hu Y, et al.A behavior-based adaptive access-mode for low-power set-associative caches in embedded systems[J].Journal of Information Processing, 2012, 20(1):26-36.
[7] Kin J, Gupta M, Mangione-Smith W H.The filter cache:an energy efficient memory structure[A].Proceedings of the 30th Annual ACM/IEEE International Symposium on Micr-oarchitecture[C].IEEE Computer Society, 1997.184-193.
[8] Yang C L, Lee C H.HotSpot cache:joint temporal and spatial locality exploitation for i-cache energy reduction[A].Proceedings of the 2004 International Symposium on Low Power Electronics and Design[C].IEEE, 2004.114-119.
[9] Fan L, Wang S, Zheng Y, et al.Low power cache architectures with hybrid approach of filtering unnecessary way accesses[A].Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores[C].ACM, 2013.93-99.
[10] 张宇弘, 王界兵, 严晓浪, 等.标志预访问和组选择历史相结合的低功耗指令cache[J].电子学报, 2004, 32(8):1286-1289. Zhang Y, Wang J.Pre-visiting tag and keeping way history to reduce power in instruction cache[J].Acta Electronica Sinica, 2004, 32(8):1286-1289.(in Chinese)
[11] 项晓燕, 陈志坚, 孟建熠, 等.基于邻行链接访问的低功耗指令高速缓存[J].浙江大学学报(工学版), 2013, 7:011. Xiang X, Chen Z.Low power instruction cache based on adjacent line linking access[J].Journal of Zhejiang University(Engineering Science), 2013, 7:011.(in Chinese)
[12] Choi J H, Kwak J W, Jhang S T, et al.Data filter cache with word selection cache for low power embedded processor[A].Proceedings of the 2013 Research in Adaptive and Convergent Systems[C].ACM, 2013.422-427.
[13] Kamble M B, Ghose K.Analytical energy dissipation models for low power caches[A].Proceedings of International Symposium on Low Power Electronics and Design [C].IEEE, 1997.143-148. |