PDF(2279 KB)
PDF(2279 KB)
PDF(2279 KB)
改进型高速高精度CORDIC算法及其在DDFS中的应用
Direct Digital Frequency Synthesizer Based on an Improved High Speed & High Precision CORDIC Algorithm
提出了一种新的选择迭代式高速高精度CORDIC（COrdinate Rotation Digital Computer）算法.基于表驱动法缩小目标旋转角度，通过改进的基本角度选择方法旁路不必要的迭代；并以移位和减法实现幅度校正，减小硬件资源消耗.设定角度误差小于10-5rad时，迭代次数减小至7次以下.在DDFS（Direct Digital Frequency Synthesizer）的应用中，利用区间压缩技术在Xilinx的FPGA中实现20位定点小数电路设计.仿真及实测结果表明，该算法幅度误差小于2×10-5，输出延时不大于43.5ns，同时硬件资源消耗不增加.
A novel optional-iteration high speed and high precision CORDIC algorithm is proposed in this paper.First the rotation is conducted with a corresponding angle based on table-driven method.Then the algorithm bypasses unnecessary iterations using a new basic angle choosing technique.And the correction is achieved by shift and subtraction to reduce hardware consumption.Calculation and simulation indicate that the new algorithm can reduce the iteration number to less than 7 when the phase error is smaller than 10-5rad.In the application of DDFS,20 fractional binary bits design is implemented in Xilinx FPGA with range reduction method.This design can reduce amplitude error to smaller than 2×10-5 for sine and cosine,cut the output delay down to 43.5ns in circuit test,and no hardware consumption increase.
坐标旋转数字计算机 / 直接数字频率合成器 / 表驱动 / 现场可编程门阵列 {{custom_keyword}} /
CORDIC(COrdinate rotation digital computer) / DDFS(direct digital frequency synthesizer) / table-driven / FPGA(field programmable gate array) {{custom_keyword}} /
[1] Tierney J,Rader C M,Gold B.A digital frequency synthesizer[J].IEEE Transactions on Audio and Electroacoustics,1971,19(1):48-57.
[2] Yang W,Hao M.A direct digital frequency synthesizer based on CORDIC algorithm implemented with FPGA[A].Proceedings of the 5th International Conference on ASIC[C].Beijing,China:IEEE,2003.2:832-835.
[3] Han W,Yousi Z,Xiaokang L.A parallel double-step CORDIC algorithm for digital down converter[A].2009 7th Annual Communication Networks and Services Research Conference (CNSR)[C].Moncton,BC,Canada:IEEE,2009.257-261.
[4] Volder J E.The CORDIC trigonometric computing technique[J].IRE Transactions on Electronic Computers,1959,Ec-8(3):330-334.
[5] 祁艳杰,刘章发.基于Parallel-CORDIC的高精度高速度直接数字频率合成器的FPGA实现[J].电子学报,2014,42(7):1392-1397. QI Yan-jie,LIU Zhang-fa.FPGA implementation of high speed and high precision direct digital frequency synthesizer based on parallel-CORDIC[J].Acta Electronica Sinica,2014,42(7):1392-1397.(in Chinese)
[6] Xin R,Zhang X,Li H,et al.An area optimized direct digital frequency synthesizer based on improved hybrid CORDIC algorithm[A].3rd International Workshop on Signal Design and Its Applications in Communications[C].Chengdu,China:IEEE,2007.243-246.
[7] Shukla R,Ray K C.Low latency hybrid CORDIC algorithm[J].IEEE Transactions on Computers,2014,63(12):3066-3078.
[8] Chuang T P,Huang C C,Hsiao S F.Design of a CORDIC-based SIN/COS intellectual property (IP) using predictable sign bits[A].Proceedings of the 27th European Solid-State Circuits Conference[C].Villach,Austria:IEEE,2001.277-280.
[9] Han L,Ko S B.High-speed parallel decimal multiplication with redundant internal encodings[J].IEEE Transactions on Computers,2013,62(5):956-968.
[10] Fei Yetai.Error Theory and Data Processing[M].Beijing:Higher Education Press,2010.66-74.(in Chinese)
[11] Hu Y H.The quantization effects of the CORDIC algorithm[J].IEEE Transactions on Signal Processing,1992,40(4):834-844.
[12] Maharatna K,Banerjee S,Grass E,et al.Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture[J].IEEE Transactions on Circuits and Systems for Video Technology,2005,15(11):1463-1474.
国家自然科学基金 (No.41274190，No.41074130，No.41327802）
/
| 〈 |
|
〉 |
