UPRFloor:一种动态可重构FPGA建模方法与布局策略

doi:10.3969/j.issn.0372-2112.2018.12.007

电子学报 ›› 2018, Vol. 46 ›› Issue (12): 2862-2869.DOI: 10.3969/j.issn.0372-2112.2018.12.007

UPRFloor:一种动态可重构FPGA建模方法与布局策略

王今雨^1,2, 伍卫国^1,2, 秦朝楠¹, 赵东方¹, 聂世强¹

1. 西安交通大学电子与信息工程学院, 陕西西安 710049;
2. 西安交通大学国家数据广播工程中心, 陕西西安 710049

收稿日期:2017-09-04 修回日期:2018-02-13 出版日期:2018-12-25
- 作者简介:
- 王今雨 男,1989年生于陕西富平,现为西安交通大学计算机系博士生.主要研究方向为可重构计算.E-mail:wjyokok@gmail.com;伍卫国 男,1963年生于江西,现为西安交通大学高性能计算机研究所博士生导师.主要研究方向为高性能计算机体系结构,云计算与嵌入式系统.E-mail:wgwu@mail.xjtu.edu.cn;秦朝楠 男,1990年生于陕西渭南,现为西安交通大学计算机系硕士研究生.主要研究方向为云计算与大数据.E-mail:413208357@qq.com;赵东方 男,1995年生于云南昆明,现为西安交通大学计算机系硕士研究生.主要研究方向为FPGA性能优化.E-mail:476337455@qq.com
- 基金资助:
- 国家重点研发计划 (No.2017YFB1001701）; 国家自然科学基金项目 (No.61672423，No.61628210）

UPRFloor: A Modeling and Floorplanner for Partially Reconfigurable FPGA Systems

WANG Jin-yu^1,2, WU Wei-guo^1,2, QIN Zhao-nan¹, ZHAO Dong-fang¹, NIE Shi-qiang¹

1.The School of Electronic and Information Engineering, Xi'an Jiaotong University, Xi'an, Shaanxi 710049, China;
2.National Data Broadcast Engineering Center, Xi'an Jiaotong University, Xi'an, Shaanxi 710049, China

Received:2017-09-04 Revised:2018-02-13 Online:2018-12-25 Published:2018-12-25
- Supported by:
- National Key Research and Development Program of China (No.2017YFB1001701); National Natural Science Foundation of China (No.61672423, No.61628210)

摘要/Abstract

摘要： 针对现场可编程门阵列（Field Programmable Gate Array，FPGA）布局过程中片上可重构资源利用率低与通信开销过高问题，本文提出了一种支持多描述模型的布局策略Union Partial Reconfiguration Floorplans（UPRFloor）.首先，该策略根据逻辑功能客观形状，定义了矩形、非矩形多描述模型，然后利用混合整数线性规划方法，从可重构资源利用率、逻辑功能间通信开销与逻辑功能内部通信开销三个方面进行多目标优化，实现了三者之间相互影响与共同作用下的最优布局方案.该策略已在FPGA芯片上进行了仿真布局，结果表明：与基于矩形模型的布局方法相比，UPRFloor布局策略在资源利用率方面最高有25.59%的提升.在Microelectronics Center of North Carolina（MCNC）标准测试集上的对比实验表明：在耗时几乎相同的情况下，UPRFloor较其它算法的布线长度最多减少了22.49%；在Software Defined Radio（SDR）测试数据中，UPRFloor在节约29.41%可重构资源的同时，布线长度节省了13.41%，从而有效降低了资源浪费与通信开销.

关键词: 现场可编程门阵列, 重构计算, 布局策略, 混合整数线性规划

Abstract: In this paper, a multi-model based floorplanner named UPRFloor is proposed to save reconfigurable resources and reduce communication overhead during the floorplanning of FPGAs. According to the shape of logical functions, a description model which can depict both rectangular and non-rectangular shapes is firstly defined. Then, the Mixed-Integer Linear Programming (MILP) ideology is used to optimize an objective function which takes the waste of resources and all kinds of communication costs into account to obtain a desirable floorplan. Finally, the UPRFloor strategy has been simulated on FPGA chips and the results show that the strategy saves reconfigurable resources as much as 25.59%. The proposed method is validated on the data set from MCNC standard benchmark. The UPRFloor reduces 22.49% global wire length at most with almost the same time-consuming as other algorithms. Experiments conducted on the SDR design also demonstrate that the strategy saves reconfigurable resources as much as 29.41% and reduces 13.41% global wire length at most, which effectively reduces the wasting of resources the communication cost.

Key words: field programmable gate array, reconfigurable computing, floorplan, mixed-integer linear programming

中图分类号:

TP301.6

王今雨, 伍卫国, 秦朝楠, 等. UPRFloor:一种动态可重构FPGA建模方法与布局策略[J]. 电子学报, 2018, 46(12): 2862-2869.

WANG Jin-yu, WU Wei-guo, QIN Zhao-nan, et al. UPRFloor: A Modeling and Floorplanner for Partially Reconfigurable FPGA Systems[J]. Acta Electronica Sinica, 2018, 46(12): 2862-2869.

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UPRFloor:一种动态可重构FPGA建模方法与布局策略

UPRFloor: A Modeling and Floorplanner for Partially Reconfigurable FPGA Systems

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