高性能并行全冗余十进制乘法器的设计

doi:10.3969/j.issn.0372-2112.2018.06.036

电子学报 ›› 2018, Vol. 46 ›› Issue (6): 1519-1523.DOI: 10.3969/j.issn.0372-2112.2018.06.036

高性能并行全冗余十进制乘法器的设计

张柳, 崔晓平, 董文雯

南京航空航天大学电子信息工程学院, 江苏南京 211106

收稿日期:2017-04-25 修回日期:2017-07-06 出版日期:2018-06-25
- 通讯作者:
- 崔晓平
- 作者简介:
- 张柳,女,1992年7月出生于江苏南通.现为南京航空航天大学研究生.主要研究方向为电路与系统.E-mail:zhangliunuaa@gmail.com
- 基金资助:
- 国家自然科学基金 (No.61404087）; 航空科学基金重点实验室类 (No.20152052025）; 南京航空航天大学研究生创新基地 (实验室）开放基金 (No.kfjj20160407）; 中央高校基本科研业务费专项资金 (No.NS2015045）

High-Performance Parallel Fully Redundant Decimal Multiplier

ZHANG Liu, CUI Xiao-ping, DONG Wen-wen

College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu 211106, China

Received:2017-04-25 Revised:2017-07-06 Online:2018-06-25 Published:2018-06-25
- Supported by:
- National Natural Science Foundation of China (No.61404087); Aeronautical Science Foundation of China, ASFC (Key Laboratory Fund) (No.20152052025); Open Fund of Postgraduate Innovation Base (laboratory) of Nanjing University of Aeronautics and Astronautics (No.kfjj20160407); Fundamental Research Funds for the Central Universities (No.NS2015045)

摘要/Abstract

摘要： 商业计算、金融分析等领域对高精度计算的需求对硬件十进制运算提出了越来越高的要求.已有的全冗余十进制乘法器由于全冗余加法器的结构复杂，已经给其性能的提升造成了瓶颈.本文优化设计了基于超载十进制数集（Overloaded Decimal Digit Set，ODDS）的全冗余ODDS加法器以降低其复杂度，并设计了一种新的基于该加法器的十进制压缩树模块.本文在部分积产生模块采用有符号的基-10编码和冗余的二-十进制（Binary Coded Decimal，BCD）编码快速产生十进制部分积.在最终积产生模块采用优化的编码转换电路快速产生BCD-8421乘积.实验结果显示所设计的并行全冗余十进制乘法器速度较快、面积较小.

关键词: 乘法器, 十进制运算, BCD编码, 冗余编码, 全冗余加法器, 编码转换

Abstract: High-performance decimal hardware arithmetic is now a high demand due to the requirement for accurate computation in fields like commercial computing and financial analysis.The performance of fully redundant decimal multiplier is limited because the circuit for fully redundant adder is complex.A modified fully redundant adder based on overloaded decimal digit set (ODDS) and a new decimal reduction tree based on fully redundant ODDS adders are proposed.The signed-digit radix-10 recoding and redundant binary coded decimal (BCD) codes are used for fast partial product generation.A recoding conversion circuit is proposed to generate BCD-8421 product fast.Comparison shows that the delay and area of the proposed decimal multiplier are small.

Key words: multiplier, decimal arithmetic, BCD coding, redundant coding, fully redundant adder, recoding conversion

中图分类号:

TN492

张柳, 崔晓平, 董文雯. 高性能并行全冗余十进制乘法器的设计[J]. 电子学报, 2018, 46(6): 1519-1523.

ZHANG Liu, CUI Xiao-ping, DONG Wen-wen . High-Performance Parallel Fully Redundant Decimal Multiplier[J]. Acta Electronica Sinica, 2018, 46(6): 1519-1523.

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高性能并行全冗余十进制乘法器的设计

High-Performance Parallel Fully Redundant Decimal Multiplier

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