基于QN旋转布局的10位500MS/s分段电流舵DAC

doi:10.3969/j.issn.0372-2112.2019.11.010

电子学报 ›› 2019, Vol. 47 ›› Issue (11): 2304-2310.DOI: 10.3969/j.issn.0372-2112.2019.11.010

基于Q^N旋转布局的10位500MS/s分段电流舵DAC

佟星元, 王超峰, 贺璐璐, 董嗣万

西安邮电大学电子工程学院, 陕西西安, 710121

收稿日期:2019-01-08 修回日期:2019-04-08 出版日期:2019-11-25
- 通讯作者:
- 佟星元
- 作者简介:
- 王超峰 男,1994年出生于山西吕梁.现为西安邮电大学电子工程学院研究生.主要研究方向包括高速数模转换器和延迟锁定环电路.E-mail:835082959@qq.com;贺璐璐 女,1992年出生于陕西省,西安邮电大学硕士,主要进行数字滤波器设计优化技术研究.E-mail:919183451@qq.com;董嗣万 男,1988年出生,西安邮电大学电子工程学院讲师,主要研究方向为模拟集成电路设计.E-mail:dsiwan@163.com
- 基金资助:
- 国家自然科学基金 (No.61674122); 陕西省重点研发计划项目 (No.2017KJXX-46); 陕西省高层次人才特殊支持计划项目

A 10-bit 500MS/s Current Steering DAC with Q^N Rotary Layout

TONG Xing-yuan, WANG Chao-feng, HE Lu-lu, DONG Si-wan

School of Electronics Engineering, Xi'an University of Posts and Telecommunications, Xi'an, Shaanxi 710121, China

Received:2019-01-08 Revised:2019-04-08 Online:2019-11-25 Published:2019-11-25
- Corresponding author:
- TONG Xing-yuan
- Supported by:
- National Natural Science Foundation of China (No.61674122); Key Research and Development Program of Shaanxi Province (No.2017KJXX-46); Special Support Project for High-level Talents of Shaanxi Province

摘要/Abstract

摘要： 针对分段电流舵数/模转换器（Digital-to-Analog Converter，DAC），通过理论分析和推导，研究电流源阵列系统失配误差和寄生效应对非线性的影响，采用电流源阵列Q^N旋转游走版图布局方案，能够减小电流源系统失配的一次误差，而且版图布线简单，由寄生效应引起的电流源失配较小，利于DAC非线性的优化.基于0.18μm CMOS，采用"6+4"的分段结构，设计了一种10位500MS/s分段电流舵DAC，流片测试结果表明，在输入频率为1.465MHz，采样速率为500MS/s的条件下，无杂散动态范围（Spurious Free Dynamic Range，SFDR）为64.9dB，有效位数（Effective Number of Bits，ENOB）为8.8 bit，微分非线性误差（Differential Non-linearity，DNL）和积分非线性误差（Integral Non-linearity，INL）分别为0.77LSB和1.12LSB.

关键词: 数/模转换器, 分段电流舵, 版图布局, 系统误差, 非线性

Abstract: According to the segmented current steering digital-to-analog converter (DAC), the influence of current mismatch and parasitics in the current array on the nonlinearity of DAC is discussed by theoretical analysis and derivation. A layout plan for the current array, Q^N rotary walk scheme is utilized for optimizing the nonlinearity of DAC. The metal connection in this layout scheme is relatively simple and the current mismatch caused by parasitic effect is small. With the segmented structure of 6 bit thermometer code and 4 bit binary code, a 10 bit DAC is realized in a 0.18μm CMOS by using the above layout plan. The measurement results show that the differential non-linearity (DNL) and the integral non-linearity (INL) of the DAC with Q^N rotary layout scheme are 0.77 LSB and 1.12 LSB. With 500MS/s sampling rate and 1.465MHz input frequency, the spurious free dynamic range (SFDR) and the effective number of bits (ENOB) are 64.9dB and 8.8bit, respectively.

Key words: digital-to-analog converter, segmented current steering, layout design, non-linearity

中图分类号:

TN495

佟星元, 王超峰, 贺璐璐, 等. 基于Q^N旋转布局的10位500MS/s分段电流舵DAC[J]. 电子学报, 2019, 47(11): 2304-2310.

TONG Xing-yuan, WANG Chao-feng, HE Lu-lu, et al. A 10-bit 500MS/s Current Steering DAC with Q^N Rotary Layout[J]. Acta Electronica Sinica, 2019, 47(11): 2304-2310.

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基于Q^N旋转布局的10位500MS/s分段电流舵DAC

A 10-bit 500MS/s Current Steering DAC with Q^N Rotary Layout

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基于QN旋转布局的10位500MS/s分段电流舵DAC

A 10-bit 500MS/s Current Steering DAC with QN Rotary Layout

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基于Q^N旋转布局的10位500MS/s分段电流舵DAC

A 10-bit 500MS/s Current Steering DAC with Q^N Rotary Layout