电子学报 ›› 2019, Vol. 47 ›› Issue (8): 1626-1632.DOI: 10.3969/j.issn.0372-2112.2019.08.004

• 学术论文 • 上一篇    下一篇

基于gm/Id参数的CMOS运算放大器设计重用方法

于浩, 郭裕顺, 李康   

  1. 杭州电子科技大学电子信息学院, 浙江杭州 310018
  • 收稿日期:2018-09-21 修回日期:2019-02-25 出版日期:2019-08-25
    • 通讯作者:
    • 郭裕顺
    • 作者简介:
    • 于浩 1996年生于黑龙江,2018年毕业于杭州电子科技大学集成电路与集成系统专业,获学士学位.主要从事模拟集成电路设计的研究.E-mail:1193483821@qq.com

A gm/Id Based Methodology for Design Reuse of CMOS Operational Amplifiers

YU Hao, GUO Yu-shun, LI Kang   

  1. School of Electronics and Information Engineering, Hangzhou Dianzi University, Hangzhou, Zhejiang 310018, China
  • Received:2018-09-21 Revised:2019-02-25 Online:2019-08-25 Published:2019-08-25

摘要: 模拟电路的设计重用是提高模拟与混合信号集成电路设计效率的重要途径.本文提出了一种基于gm/Id参数的不同工艺之间同一结构电路的设计移植方法.方法的基本思想是保持移植前后电路中部分关键MOS管的gm/Id参数,从而使移植后电路的性能也基本保持不变.介绍了基于BSIM等模型的gm/Id匹配及移植电路参数确定方法.给出了一个Miller补偿两级运放及一个折叠共源共栅运放从0.35μm工艺到0.18μm、0.13μm、90nm工艺的移植仿真结果.与现有方法相比,本文方法可以更小的计算代价,得到性能基本相同、但功耗与面积缩减的电路.

关键词: 模拟集成电路设计, 模拟IP, 设计重用, 工艺移植

Abstract: Design reuse is an important means to increase the productivity of analog and mixed-siganl IC designs.A gm/Id based resizing methodology for CMOS OpAmp's is proposed in this paper.The basic idea is to preserve the gm/Id parameters of some crucial transistors in the circuit with the aim of the approximate performance preservation of the resized circuit.The method to accurately match the gm/Id parameters based on the BSIM like model between the resized and the original circuit is presented.The resizing experiments of a two-stage Miller compensated OpAmp and a folded cascode OpAmp for the process migration from a 0.35 μm CMOS technology to a 0.18 μm,0.13 μm,90nm one have been performed to validate the proposed method.The simulation results show that the method generates the resized circuits with almost the same performance but reduced power and area consumption at a lower computational cost compared with the existing approaches.

Key words: analog IC design, analog IP, design reuse, process migration

中图分类号: