[1] Schwank J R,Shaneyfelt M R,Dodd P E.Radiation hardness assurance testing of microelectronic devices and integrated circuits:Radiation environments,physical mechanisms,and foundations for hardness assurance[J].IEEE Transactions on Nuclear Science,2013,60(3):2074-2100. [2] Zick K M,Hayes J P.High-level vulnerability over space and time to insidious soft errors[A].IEEE International High Level Design Validation and Test Workshop[C].Nevada,USA:IEEE,2008.161-168. [3] 宋超.逻辑电路软错误率评估模型设计与实现[D].长沙:国防科学技术大学,2010. SONG C.Design and implementation of a soft error rate estimation model in logic circuits[D].Changsha:National University of Defense Technology,2010.(in Chinese) [4] Zhu X,Deng X,Baumann R,et al.A quantitative assessment of charge collection efficiency of N+and P+diffusion areas in terrestrial neutron environment[J].IEEE Transactions on Nuclear Science,2007,54(6):2156-2161. [5] Watkins A,Tragoudas S.Radiation hardened latch designs for double and triple node upsets[J].IEEE Transactions on Emerging Topics in Computing,2020,8(3):616-626. [6] Lin S,Kim Y B,Lombardi F.Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset[J].IEEE Transactions on Device and Materials Reliability,2011,12(1):68-77. [7] D'Alessio M,Ottavi M,Lombardi F.Design of a nanometric CMOS memory cell for hardening to a single event with a multiple-node upset[J].IEEE Transactions on Device and Materials Reliability,2012,14(1):127-132. [8] He Q,Yan A,Lai C,et al.Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS[A].IEEE International Symposium on Circuits and Systems (ISCAS)[C].Florence,IT:IEEE,2018.1-5. [9] Mavis D G,Eaton P H.Soft error rate mitigation techniques for modern microcircuits[A].IEEE International Reliability Physics Symposium Proceedings,40th Annual (Cat.No.02CH37320)[C].Dallas,USA:IEEE,2002.216-225. [10] Calin T,Nicolaidis M,Velazco R.Measurements and analysis of SER-tolerant latch in a 90nm dual-VT CMOS process[J].IEEE Tran.On Nuclear Science,1996.2874-2878. [11] Yan A,Feng X,Hu Y,et al.Design of a triple-node-upset self-recoverable latch for aerospace applications in harsh radiation environments[J].IEEE Transactions on Aerospace and Electronic Systems,2020,56(2):1163-1171. [12] Fazeli M,Miremadi S G,Ejlali A,et al.Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies[J].IET Computers & Digital Techniques,2009,3(3):289-303. [13] Katsarou K,Tsiatouhas Y.Double node charge sharing SEU tolerant latch design[A].IEEE 20th International On-Line Testing Symposium(IOLTS)[C].Girona,ES:IEEE,2014.122-127. [14] Liu X.Multiple node upset-tolerant latch design[J].IEEE Transactions on Device and Materials Reliability,2019,19(2):387-392. [15] Sheshadri V B,Bhuva B L,Reed R A,et al.Effects of multi-node charge collection in flip-flop designs at advanced technology nodes[A].IEEE International Reliability Physics Symposium[C].California,USA:IEEE,2010.1026-1030. [16] Li T,Yang H,Cai G,et al.A CMOS triple inter-locked latch for SEU insensitivity design[J].IEEE Transactions on Nuclear Science,2014,61(6):3265-3273. [17] Yan A,Lai C,Zhang Y,et al.Novel low cost,double-and-triple-node-upset-tolerant latch designs for nano-scale CMOS[J].IEEE Transactions on Emerging Topics in Computing,2018,PP(99):1-1. [18] Kumar C I,Anand B.A highly reliable and energy-efficient triple-node-upset-tolerant latch design[J].IEEE Transactions on Nuclear Science,2019,66(10):2196-2206. |