32nm CMOS工艺三点翻转自恢复锁存器设计

doi:10.12263/DZXB.20200530

电子学报 ›› 2021, Vol. 49 ›› Issue (2): 394-400.DOI: 10.12263/DZXB.20200530

32nm CMOS工艺三点翻转自恢复锁存器设计

黄正峰¹, 潘尚杰¹, 曹剑飞¹, 宋钛¹, 欧阳一鸣², 梁华国¹, 倪天明³, 鲁迎春¹

1. 合肥工业大学电子科学与应用物理学院, 安徽合肥 230601;
2. 合肥工业大学计算机与信息学院, 安徽合肥 230601;
3. 安徽工程大学电气工程学院, 安徽芜湖 241000

收稿日期:2020-06-02 修回日期:2020-09-27 出版日期:2021-02-25
- 通讯作者:
- 鲁迎春
- 作者简介:
- 黄正峰 男,1978年2月出生,安徽无为人.2009年获合肥工业大学计算机应用技术专业工学博士学位,现为合肥工业大学微电子学院教授、博士生导师,主要研究方向为数字集成电路的硬件容错、星载SoC芯片的抗辐射加固等.E-mail:huangzhengfeng@139.com;潘尚杰 男,1997年4月出生,安徽繁昌人.硕士研究生,主要研究方向为数字集成电路的硬件容错.E-mail:psjhfut@163.com
- 基金资助:
- 国家自然科学基金 (No.61874156，No.61874157，No.61904001）; 安徽省自然科学基金 (No.1908085QF272）

Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology

HUANG Zheng-feng¹, PAN Shang-jie¹, CAO Jian-fei¹, SONG Tai¹, OUYANG Yi-ming², LIANG Hua-guo¹, NI Tian-ming³, LU Ying-chun¹

1. School of Electronic Science&Applied Physics, Hefei University of Technology, Hefei, Anhui 230601, China;
2. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230601, China;
3. College of Electrical Engineering, Anhui Polytechnic University, Wuhu, Anhui 241000, China

Received:2020-06-02 Revised:2020-09-27 Online:2021-02-25 Published:2021-02-25
- Corresponding author:
- LU Ying-chun
- Supported by:
- National Natural Science Foundation of China (No.61874156, No.61874157, No.61904001); Natural Science Foundation of Anhui Province (No.1908085QF272)

摘要/Abstract

摘要： CMOS工艺的特征尺寸不断缩减，电荷共享效应诱发的单粒子三点翻转成为研究热点.本文提出了一种单粒子三点翻转自恢复的抗辐射加固锁存器：Hydra-DICE（Dual Interlocked Storage Cell）.该锁存器基于24个同构的交叉耦合单元（Cross-Coupled Elements，CCE）排列成阵列结构.当内部任意三个节点同时发生单粒子翻转时，该锁存器都可以自行恢复到正确的逻辑值.与具有等效三点自恢复能力的TNURL（Triple Node Upset Self-Recoverable Latch）锁存器相比，该Hydra-DICE锁存器面积开销降低50%，延迟降低48.28%，功耗降低25%，功耗延迟积降低61.21%.仿真结果表明，该加固锁存器在容错性能、面积开销、延迟和功耗方面取得了很好的折中.

关键词: 锁存器, 单粒子翻转, 双模互锁存储单元, 抗辐射加固, 自恢复

Abstract: The feature size of CMOS technology is continuously shrinking, and the single event triple-node-upset induced by the charge sharing effect has become a research hotspot. This paper proposed a single event triple-node-upset self-recovery radiation-hardened latch: Hydra-DICE. The latch is arranged in an array structure based on 24 homogeneous cross-coupled elements (CCE). When a single event upset occurs at any three internal nodes concurrently, Hydra-DICE can realize the function of self-recovery to the correct logical value. Compared with the TNURL latch which has the equivalent triple-node-upset self-recovery capability, the Hydra-DICE latch has a 50% reduction in area overhead, a 48.28% reduction in delay, a 25.00% reduction in power consumption, and a 61.21% reduction in power consumption delay product. The simulation results show that the hardened latch has made a good compromise in fault tolerance performance, area overhead,delay and power.

Key words: latch, single event upset, dual interlocked storage cell, radiation-hardened, self-recovery

中图分类号:

TN43

黄正峰, 潘尚杰, 曹剑飞, 等. 32nm CMOS工艺三点翻转自恢复锁存器设计[J]. 电子学报, 2021, 49(2): 394-400.

HUANG Zheng-feng, PAN Shang-jie, CAO Jian-fei, et al. Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology[J]. Acta Electronica Sinica, 2021, 49(2): 394-400.

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32nm CMOS工艺三点翻转自恢复锁存器设计

Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology

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