电子学报 ›› 2017, Vol. 45 ›› Issue (12): 2890-2895.DOI: 10.3969/j.issn.0372-2112.2017.12.009

• 学术论文 • 上一篇    下一篇

采用环型运放的12-bit 40-MS/s采样保持电路设计实现

魏子辉1,2, 黄水龙1,2, 单强1,2   

  1. 1. 中国科学院微电子研究所, 北京 100029;
    2. 新一代通信射频芯片技术北京市重点实验室, 北京 100029
  • 收稿日期:2016-07-15 修回日期:2017-06-14 出版日期:2017-12-25
    • 通讯作者:
    • 魏子辉
    • 作者简介:
    • 黄水龙,男,1975年出生于湖北通城,博士,副研究员,研究方向为高性能模拟/射频CMOS集成电路;单强,男,1983年9月出生于辽宁葫芦岛,硕士,助理研究员,研究方向为模拟CMOS集成电路设计.
    • 基金资助:
    • 国家科技重大专项 (No.2014ZX02302007); 青年科学基金 (No.61404166)

Implementation of a 12-bit 40-MS/s Sample-and-Hold Circuit with a Ring Amplifier

WEI Zi-hui1,2, HUANG Shui-long1,2, SHAN Qiang1,2   

  1. 1. Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China;
    2. Beijing Key Laboratory of Radio Frequency IC Technology for Next Generation Communications, Beijing 100029, China
  • Received:2016-07-15 Revised:2017-06-14 Online:2017-12-25 Published:2017-12-25

摘要: 为了保证模数转换器转换速度和精度,本文基于0.18微米工艺,设计实现了一款应用于12-bit 40-MS/s流水线ADC前端的采样保持电路.所采用的环型结构运放,可以简化设计、且占用面积小;同时,采用绝缘体上硅工艺,可以消除栅压自举开关中开关管的衬偏效应,改善开关的线性度,提高采样保持电路的性能.采样保持电路面积是0.023平方毫米.测试结果表明:在1.5V供电电压下,采样保持电路功耗是3.5mW;在1MHz输入频率、40MHz采样频率下,该采样保持电路无杂散动态范围可以达到76.85dB,满足12-bit 40-MS/s流水线模数转换器应用需求.

关键词: 采样保持电路, 绝缘体上硅工艺, 运放, 栅压自举开关, 无杂散动态范围

Abstract: In order to keep the analog to digital converter's speed and precision,a sample-and-hold(S/H) circuit for a 12-bit 40-MS/s pipeline ADC is designed and fabricated using a 0.18 micrometer process.The proposed amplifier can simplify the design and occupies smaller area.The substrate bias effect of the switch transistor used in the bootstrapped switch can be eliminated with the silicon-on-insulator (SOI) process,which can increase the linearity of bootstrapped switch and improve the performance of the S/H circuit.The S/H circuit occupies an area of 0.023 square millimeter.Measurement results show that the S/H circuit operates at a 1.5 V supply and consumes 3.5mW,and the spurious free dynamic range is 76.85 dB for a 1 MHz input signal with 40 MS/s sampling rate.The S/H circuit meets the requirement of the 12-bit 40-MS/s pipeline analog to digital converter.

Key words: S/H circuit, SOI process, amplifier, bootstrapped switch, SFDR

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