基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET

doi:10.3969/j.issn.0372-2112.2018.08.031

电子学报 ›› 2018, Vol. 46 ›› Issue (8): 2026-2029.DOI: 10.3969/j.issn.0372-2112.2018.08.031

基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET

刘佳佳, 刘英坤, 谭永亮, 张力江, 崔玉兴

中国电子科技集团公司第十三研究所, 河北石家庄 050051

收稿日期:2017-12-13 修回日期:2018-03-30 出版日期:2018-08-25
- 通讯作者:
- 刘佳佳
- 作者简介:
- 刘英坤 男,1965年生于河北新乐,博士,研究员,硕士生导师,河北半导体研究所副总工程师,长期从事微波功率器件、半导体分立器件及微电子工艺技术研究.E-mail:ykliuyk@sina.com

1.2kV 4H-SiC DMOSFET with Phosphorous Passivated Gate Dielectric

LIU Jia-jia, LIU Ying-kun, TAN Yong-liang, ZHANG Li-jiang, CUI Yu-xing

The 13 th Research Institute, CETC, Shijiazhuang, Hebei 050051, China

Received:2017-12-13 Revised:2018-03-30 Online:2018-08-25 Published:2018-08-25

摘要/Abstract

摘要： 本文对比了NO退火和磷掺杂两种栅钝化工艺，其中磷钝化采用了平面扩散源进行掺杂，通过C-V特性进行了4H-SiC/SiO₂界面特性评价，使用Terman法分析计算获得距导带底0.2-0.4eV范围内界面态密度.结果表明引入磷比氮能更有效降低界面态密度，提高沟道载流子迁移率.其次，对比了两种栅钝化工艺制备的4H-SiC DMOSFET器件性能，实验表明采用磷钝化工艺处理的器件性能更优.最后，基于磷掺杂钝化工艺首次制备出击穿电压为1200V、导通电阻为20mΩ、漏源电流为75 A、阈值电压为2.4V的4H-SiC DMOSFET.

关键词: 4H-SiC MOSFET, 4H-SiC/SiO₂界面, 磷钝化, 界面态密度

Abstract: To improve the 4H-SiC/SiO₂ interface quality phosphorous-doped technology and nitrogen-annealed technology were introduced.The phosphorous atoms were introduced into the 4H-SiC/SiO₂ interface by thermal annealing with a planar diffusion source (PDS).Current-voltage test was used to characterize the interface quality.To obtain the interface state density (D_it) lying energetically within 0.2eV-0.4eV of the conduction band edge (E_c),the C-V data was analyzed by using Terman method.It is apparent that the phosphorous-doped technology can reduce the interface state density near the conduction band of 4H-SiC effectively and increase the channel mobility and decrease the on resistance.Compared with NO passivated devices,P-doped devices have better performance.What's more,this technology has been applied to fabricate 1.2kV 4H-SiC DMOSFET firstly.Fabricated devices show a significant improvement with an on resistance of 20m Ω,drain-source current of 75A,threshold voltage of 2.4V.

Key words: 4H-SiC MOSFET, 4H-SiC/SiO₂ interface, phosphorous passivation, interface states

中图分类号:

TN304.0

刘佳佳, 刘英坤, 谭永亮, 张力江, 崔玉兴. 基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET[J]. 电子学报, 2018, 46(8): 2026-2029.

LIU Jia-jia, LIU Ying-kun, TAN Yong-liang, ZHANG Li-jiang, CUI Yu-xing. 1.2kV 4H-SiC DMOSFET with Phosphorous Passivated Gate Dielectric[J]. Acta Electronica Sinica, 2018, 46(8): 2026-2029.

参考文献

[1] Saddow S E,Agarwal A.Advances in Silicon Carbide Processing and Applications[M].Boston:Artech House,2004.1-4.
[2] Afanasev V V,Bassler M,et al.Intrinsic SiC/SiO₂ interface states[J].physica status solidi,1994,162:321-337.
[3] Li H F,Dimitrijev S,Harrison H B.Improved reliability of NO-nitrided SiO₂ grown on p-type 4H-SiC[J].IEEE Electron Device Letters,1998,19(8):279-281.
[4] Chung G Y,Tin C C,et al.Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide[J].IEEE Electron Device Letters,2001,22(4):176-178.
[5] Yang X Y,Lee B,Misra V.Electrical characteristics of SiO₂ deposited by atomic layer deposition on 4H-SiC after nitrous oxide anneal[J].IEEE Transactions on Electron Devices,2016,63(7):2826-2830.
[6] Lu C Y,Tsuji T,et al.Effect of process variations and ambient temperature on electron mobility at the SiO₂/4H-SiC interface[J].IEEE Electron Device Letters,2003,50(7):1582-1588.
[7] Sharma Y K,Ahyi A C,et al.Phosphorous passivation of the SiO₂/4H-SiC interface[J].Solid State Electronics,2012,68:103-107.
[8] Yano H,Knanfuji N,et al.Threshold voltage instability in 4H-SiC MOSFETs with phosphorus-doped and nitrided gate oxides[J].IEEE Transactions on Electron Devices,2015,62(2):324-332.
[9] 朱巧智,王德君,赵亮.SiO₂/SiC界面的Wet-ROA改性机理研究[J].固体电子学研究与进展,2009,29(3):339-342 Zhu Q Z,Wang D J,ZHAO L.The mechanism of wet-ROA process in improving SiO₂/SiC interface electrical properties[J].Research & Progerss of SSE State Electronics,2009,29(3):339-342.(in Chinese)
[10] 王晓琳,刘冰冰,秦富庆,等.氮氢混合等离子体处理对SiC MOS电容可靠性的影响[J].固体电子学研究与进展,2016,36(1):71-77. Wang X L,Liu B B,et al.The effect of NH mixed plasma treatment on the reliability of SiC MOS capacitors[J].Research & Progerss of SSE State Electronics,2016,36(1):71-77.(in Chinese)
[11] Terman L M.An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes[J].Solid-State Electronics,1962,5(5):285-299.
[12] Cree.Silicon Carbide Power MOSFET C2M TM MOSFET Technology:C2M0040120D[OL].https://www.wolfspeed.com/downloads/dl/file/id/165/product/9/c2 m0040120d.pdf.

基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET

1.2kV 4H-SiC DMOSFET with Phosphorous Passivated Gate Dielectric

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 1

编辑推荐

Metrics