量子全加器设计

doi:10.3969/j.issn.0372-2112.2019.09.007

电子学报 ›› 2019, Vol. 47 ›› Issue (9): 1863-1867.DOI: 10.3969/j.issn.0372-2112.2019.09.007

量子全加器设计

常丽, 朱宇祥, 蒋辉

沈阳工业大学信息科学与工程学院, 辽宁沈阳 110870

收稿日期:2018-11-20 修回日期:2019-03-20 出版日期:2019-09-25
- 作者简介:
- 常丽女,1971年生于辽宁省沈阳市.博士,现为沈阳工业大学信息科学与工程学院副教授,博士生导师,主要研究方向为智能感知与精密测控,智能仪器及网络化测控系统.E-mail:changlianli@163.com;朱宇祥 男,1994年生于安徽省宿州市.现为沈阳工业大学信息科学与工程学院硕士研究生.主要研究方向精密测控及网络化智能测控系统.E-mail:sgdjiance2016@163.com
- 基金资助:
- 沈阳市科技局科研计划项目 (No.F16-205-1-11）

Design of Quantum Full Adder

CHANG Li, ZHU Yu-xiang, JIANG Hui

School of Information Science and Engineering, Shenyang University of Technology, Shenyang, Liaoning 110870, China

Received:2018-11-20 Revised:2019-03-20 Online:2019-09-25 Published:2019-09-25
- Supported by:
- Scientific Research Project of Shenyang Science and Technology Bureau (No.F16-205-1-11)

摘要/Abstract

摘要： 量子全加器是量子计算机的基本单元，为了减少能耗，降低构造成本及物理实现难度，本文提出一种新型n位量子全加器，使用3n个CNOT（Controlled NOT）门和2n-1个Toffoli门实现n位量子加减法，采用超前进位方式，不含进位输入，通过最高溢出标志位判断加法的进位和减法的正负号，标志位不参与高低位计算，不增加电路延时，适合n位量子并行计算.随机生成4、8、16和32位数分别进行加减仿真操作，验证了全加器的正确性.该全加器量子代价较低，结构简单，有利于提高集成电路规模和集成度.

关键词: 可逆逻辑电路, 量子全加器, 超前进位, 量子代价, 电路能耗, 量子计算机

Abstract: Quantum full adder is the basic elements of quantum computers, in order to reduce the energy loss and cut the construction cost and the difficulty of physical realization. The paper proposes a new type of n-bit quantum full adder which uses 3n CNOT(Controlled NOT) Gates and 2n-1 Toffoli gates to implement n-bit quantum addition and subtraction, adopts the carry look-ahead mode without carry input,and judges the carry of addition and positive and negative sign of subtraction with the highest overflow mark bit that does not participate in the calculation of high and low bit, which does not increase time delay of the circuit and suits for n-bit quantum parallel operation. The simulation operation with random number of 4,8,16 and 32 digits verifies the correctness of the full adder separately. The low quantum cost and simple circuit structure of the quantum full adder is helpful to improve the size and integration of integrated circuits.

Key words: reversible logic circuit, quantum full adder, carry look-ahead, quantum cost, circuit energy consumption, quantum computer

中图分类号:

TP302.2

常丽, 朱宇祥, 蒋辉. 量子全加器设计[J]. 电子学报, 2019, 47(9): 1863-1867.

CHANG Li, ZHU Yu-xiang, JIANG Hui . Design of Quantum Full Adder[J]. Acta Electronica Sinica, 2019, 47(9): 1863-1867.

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量子全加器设计

Design of Quantum Full Adder

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