基于电压毛刺故障扰动的分组密码安全性度量方法研究

doi:10.12263/DZXB.20200514

电子学报 ›› 2021, Vol. 49 ›› Issue (3): 417-423.DOI: 10.12263/DZXB.20200514

• 学术论文 • 下一篇

基于电压毛刺故障扰动的分组密码安全性度量方法研究

欧庆于, 罗芳, 吴晓平, 杨鹏

海军工程大学信息安全系, 湖北武汉 430033

收稿日期:2020-05-28 修回日期:2020-08-06 出版日期:2021-03-25
- 通讯作者:
- 罗芳
- 作者简介:
- 欧庆于 男,1978年生于江西靖安,现为海军工程大学信息安全系副教授,获军队科技进步二等奖3项,主要研究方向为密码应用安全性测评、旁路攻击防御.E-mail:ouqingyv@163.com;吴晓平 男,1961年生于山西新绛,现为海军工程大学信息安全系教授、博士生导师,主要研究领域为信息安全、系统决策.E-mail:wxp8@sohu.com;杨鹏男,1996年2月生于湖南岳阳,现为海军工程大学信息安全系硕士研究生,主要研究方向为密码芯片安全性评估.E-mail:849593165@qq.com
- 基金资助:
- 国家自然科学基金 (No.61672531）; 保密通信国防科技重点实验室基金 (No.614210301030117）

Research on the Metric Method for the Security of the Block Cipher Based on the Voltage Glitch Fault Disturbance

OU Qing-yu, LUO Fang, WU Xiao-ping, YANG Peng

Department of Information Security, Naval University of Engineering, Wuhan, Hubei 430033, China

Received:2020-05-28 Revised:2020-08-06 Online:2021-03-25 Published:2021-03-25

摘要/Abstract

摘要： 随着信息体系对抗强度的升级，网络空间已演变为由各类信息平台及控制网络互联而成的复杂网电环境，所面临的安全威胁日趋复杂.作为网络空间安全的基石，各类密码算法实现不可避免地受到由环境引入或攻击者恶意施加的故障扰动影响，进而引发密码安全性问题.本文以电压毛刺故障扰动手段为基础，对分组密码算法实现的故障产生机理及安全扰动机制进行了分析和研究；构建了用于刻画密码电路故障传播概率性波动模型；结合不可区分性理论、活动字节传播概率的统计分布技术，提出了能够充分反映故障扰动场景下分组密码实际安全特性的度量框架.实验表明，该度量框架能够充分反映实际故障概率传播特性与攻击者区分优势之间的关联性，并对分组密码实现在遭受故障攻击下的安全性实施客观分析.

关键词: 电压毛刺, 故障注入, 故障扰动, 分组密码, 安全性分析, 信息泄露

Abstract: With the upgrade of the information system confrontation,the cyberspace has developed to a complicated network electricity environment,composed of kinds of interconnected information platforms and control networks.Its security threats has been more complicated.As the security base of the cyberspace,the fault disturbance to the implementation of the cipher,caused by the environment and the malicious attacker,can not be avoided,so the security problem of the cipher will be induced.In this paper,based on the voltage glitch fault injection,the fault generation and the security disturbance mechanism of the block cipher chip,is analyzed.The fluctuant model,used for characterizing the fault propagation probability of the cipher chip,is constructed.Applying the indistinguishable theory,and the statistical distribution of the propagation probability to the active bytes,the metric model of the actual physical security for the block cipher chip,is proposed.It is experimented that,the relevance,between the actual fault propagation probability and the distinguish advantage,can be reflected by the model,so the security of the block cipher,in the scene of the fault attack,can be analyzed objectively.

Key words: voltage glitch, fault injection, fault disturbance, block cipher, security evaluation, information leakage

中图分类号:

TP309.1

欧庆于, 罗芳, 吴晓平, 杨鹏. 基于电压毛刺故障扰动的分组密码安全性度量方法研究[J]. 电子学报, 2021, 49(3): 417-423.

OU Qing-yu, LUO Fang, WU Xiao-ping, YANG Peng. Research on the Metric Method for the Security of the Block Cipher Based on the Voltage Glitch Fault Disturbance[J]. Acta Electronica Sinica, 2021, 49(3): 417-423.

参考文献

[1] Zussa L,Dutertre J M,Clediere J,Robisson B,Tria A.Investigation of timing constraints violation as a fault injection means[A].XVⅡ Conference on Design of Circuits and Integrated Systems[C].Santander,Spain:IEEE,2012.63-71.
[2] Zussa L,Dutertre J M,Clediere J,Robisson B.Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter[A].IEEE International Symposium on Hardware-oriented Security & Trust[C].Arlington,USA:IEEE,2014.151-159.
[3] Zussa L,Dutertre J M,Clediere J,Tria A.Power supply glitch induced faults on FPGA:an in-depth analysis of the injection mechanism[A].IEEE 19th International On-line Testing Symposium[C].Chania,Greece:IEEE,2013.73-81.
[4] Flynn C O.Fault Injection Using Crowbars on Embedded Systems[DB/OL].http://eprint.iacr.org/2016/810.pdf,2016.
[5] Boher B N,Beroulle V,Hly D,Damiens J,Candelier P.Clock generator behavioral modeling for supply voltage glitch attack effects analysis[J].Microprocessors & Microsystems,2016,47(PA):37-43.
[6] Vincent I,Robert S,Florian U.Your rails cannot hide from localized EM:How dual-rail logic fails on FPGAs[A].Cryptographic Hardware and Embedded Systems-CHES 2017[C].Taipei,China:Springer,2017.403-424.
[7] Krautter J,Dennis R E G,Tahoori M B.FPGA hammer:Remote voltage fault attacks on shared FPGAs,suitable for DFA on AES[A].Cryptographic Hardware and Embedded Systems-CHES 2018[C].Amsterdam,the Netherlands:Springer,2018.44-68.
[8] Zhang Fan,Lou Xiaoxuan,Zhao Xinjie,Bhasin S,He Wei,Ding Ruyi,Samiya Q,Ren Kui.Persistent fault analysis on block ciphers[A].Cryptographic Hardware and Embedded Systems-CHES 2018[C].Amsterdam,the Netherlands:Springer,2018.150-172.
[9] Lashermes R,Reymond G,Dutertre J,Fournier J,Robisson B,Tria A.A DFA on AES based on the entropy of error distributions[A].Fault Diagnosis and Tolerance in Cryptography-FDTC 2012[C].Leuven,Belgium:Springer,2012.34-43.
[10] Fuhr T,Jaulmes E,Lomn V,Thillard A.Fault attacks on AES with faulty ciphertexts only[A].Fault Diagnosis and Tolerance in Cryptography-FDTC 2013[C].Santa Barbara:Springer,CA,2013.108-118.
[11] 欧庆于,罗芳,叶伟伟,周学广.分组密码算法抗故障攻击能力度量方法研究[J].电子与信息学报,2017,39(5):1266-1270. Ou Qing-yu,Luo Fang,Ye Wei-wei,Zhou Xue-guang.Metric for defences against fault attacks of block ciphers[J].Journal of Electronics&Information Technology,2017,39(5):1266-1270.(in Chinese)
[12] Sayandeep S,Debdeep M,Pallab D.ExpFault:An automated framework for exploitable fault characterization in block ciphers[J].Journal of Cryptographic Engineering,2019,9:203-219.
[13] Behzad Razavi.Fundamentals of Microelectronics[M].Boston:Wiley,2008.796-801.
[14] Dziembowski S,Pietrzak K.Leakage-resilient cryptography[A].49th Annual IEEE Symposium on Foundations of Computer Science[C].Philadelphia,PA,USA:IEEE,2008.293-302.
[15] Sun Bing,Liu Meicheng,Guo Jian,Qu Longjiang,Rijmen V.New insights on AES-like SPN ciphers[A].2016 International Cryptology Conference[C].Santa,Barbara,UCSB:Springer,2016.605-624.
[16] Chen Shan,Steinberger J.Tight security bounds for key-alternating ciphers[A].33rd Annual International Conference on the Theory and Applications of Cryptographic Techniques[C].Copenhagen,Denmark:Springer,2014.116-124.
[17] Srivastava A,Sylvester D,Blaauw D.Statistical Analysis and Optimization for VLSI:Timing and Power[M].Ann Arbor:Springer,2005.114-118.
[18] Grassi L,Rechberger C,Ronjom S.A new structural-differential property of 5-round AES[A].36th Annual International Conference on the Theory and Applications of Cryptographic Techniques[C].Paris,France:Springer,2017.289-317.
[19] Grassi L,Rechberger C.Rigorous Analysis of Truncated Differentials for 5-round AES[DB/OL].https://eprint.iacr.org/2018/182.pdf,2018.
[20] Bao Z,Guo J,List E.Extended Expectation Cryptanalysis on Round-reduced AES[DB/OL].https://eprint.iacr.org/2019/622.pdf,2019.
[21] Sakiyama K,Li Yang,Iwamoto M,Ohta K.Information-theoretic approach to optimal differential fault analysis[J].IEEE Transactions on Information Forensics and Security,2012,7(1):109-120.

基于电压毛刺故障扰动的分组密码安全性度量方法研究

Research on the Metric Method for the Security of the Block Cipher Based on the Voltage Glitch Fault Disturbance

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

[1]	赵耿, 马英杰, 陈磊, 董有恒, 侯艳丽. 基于扰动时空混沌系统的动态S盒设计[J]. 电子学报, 2022, 50(8): 2037-2042.
[2]	胡文文, 周日贵. 基于d维单个量子态的半量子密钥分发方案[J]. 电子学报, 2022, 50(5): 1025-1032.
[3]	王鹏, 邹彬, 刘金枝, 周丹阳. 基于Xilinx型FPGA系统单粒子效应评估方法研究[J]. 电子学报, 2022, 50(11): 2716-2721.
[4]	蔡莹, 朱翔, 王舰, 李昊远, 韩建伟. 基于激光注入的FPGA加密防护设计验证研究[J]. 电子学报, 2022, 50(10): 2381-2386.
[5]	郑秋华, 胡程楠, 崔婷婷, 申延召, 曾英佩, 吴铤. 一种基于概率分析的DHR模型安全性分析方法[J]. 电子学报, 2021, 49(8): 1586-1598.
[6]	马宿东, 金晨辉, 关杰. 一类ARIA型扩散结构分支数的研究[J]. 电子学报, 2020, 48(3): 449-455.
[7]	李航, 任炯炯, 陈少真. 减轮LEA密码算法的积分攻击[J]. 电子学报, 2020, 48(1): 17-27.
[8]	王念平. 一类分组密码变换簇抵抗线性密码分析的安全性评估[J]. 电子学报, 2020, 48(1): 137-142.
[9]	宋云. 基于GHZ态局域测量的量子秘密共享[J]. 电子学报, 2019, 47(7): 1443-1448.
[10]	刘威, 蒋烈辉, 常瑞. 强物理不可克隆函数的侧信道混合攻击[J]. 电子学报, 2019, 47(12): 2639-2646.
[11]	杜怡然, 南龙梅, 戴紫彬, 李伟. 可重构分组密码逻辑阵列加权度量模型及高能效映射算法[J]. 电子学报, 2019, 47(1): 82-91.
[12]	吴涛, 景晓军. 一种强不可伪造无证书签名方案的密码学分析与改进[J]. 电子学报, 2018, 46(3): 602-606.
[13]	王晶, 荣金叶, 周继芹, 于航, 申娇, 张伟功. 软硬件协同设计的SEU故障注入技术研究[J]. 电子学报, 2018, 46(10): 2534-2538.
[14]	冯晓, 李伟, 戴紫彬, 马超, 李功丽. 面向分组密码的可重构异构多核并行处理架构[J]. 电子学报, 2017, 45(6): 1311-1320.
[15]	王寿成, 严迎建, 徐进辉. 基于流体系结构的高效能分组密码处理器研究[J]. 电子学报, 2017, 45(4): 937-943.