[1] BANERJEE K,SOURI S J,KAPUR P,et al.3-D ICs:a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration[J].Proceedings of the IEEE,2001,89(5):602-633. [2] 常郝,梁华国,等.一种3D堆叠集成电路中间绑定测试时间优化方案[J].电子学报,2015,43(2):393-398. CHANG H,LIANG H-G,et al.Optimization scheme for mid-bond test time on 3D-stacked ICs[J].Acta Electronica Sinica,2015,43(2):393-398.(in Chinese) [3] 神克乐,虞志刚,白宇.基于TSV绑定的三维芯片测试优化策略[J].电子学报,2016,44(1):155-159. SHEN K-L,YU Z-G,BAI Y.Optimization strategy for TSV-based 3D SoC testing[J].Acta Electronica Sinica,2016,44(1):155-159.(in Chinese) [4] EGHBAL A,YAGHINI P M,et al.Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip[J].IEEE Transactions on Computers,2015,64(12):3591-3604. [5] 欧阳一鸣,孙成龙,等.3D NoC关键通信部件容错方法研究综述[J].电子学报,2016,44(12):3053-3063. OUYANG Y-M,SUN C-L,et al.Fault-tolerant method of critical communication components in 3D NoC:A review[J].Acta Electronica Sinica,2016,44(12):3053-3063.(in Chinese) [6] LIU X,CHEN Q,et al.Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)[A].Proceeding of the 59th Electronic Components and Technology Conference[C].San Diego:IEEE,2009.624-629. [7] MARINISSEN E,ZORIAN Y.Testing 3D chips containing through-silicon vias[A].Proceedings of Test Conference[C].Austin:IEEE,2009.1-11. [8] JIANG L,XU Q,EKLOW B.On Effective Through-silicon via repair for 3D-stacked ICs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2013,32(4):559-571. [9] XU Q,CHEN S,XU X,et al.Clustered fault tolerance TSV planning for 3D integrated circuits[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2017,36(8):1287-1300. [10] LO W,CHI K,HWANG T,et al.Architecture of ring-based redundant TSV for clustered faults[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2016,24(12):3437-3449. [11] NI T,LIANG H,NIE M,et al.A region-based through-silicon via repair method for clustered faults[J].IEICE Transactions on Electronics,2017,100(12):1108-1117. [12] WANG Q,LIU Z,JIANG J,et al.A new cellular-based redundant TSV structure for clustered faults[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2019,27(2):458-467. [13] LEE I,CHEONG M,KANG S.Highly reliable redundant TSV architecture for clustered faults[J].IEEE Transactions on Reliability,2019,68(1):237-247. [14] GOLDBERG A G,RAO S.Beyond the flow decomposition barrier[J].Journal of the ACM,1998,45(5):783-797 [15] 段凡丁.关于最短路径的SPFA快速算法[J].西南交通大学学报,1994,29(2):207-212. DUAN F.A faster algorithm for shortest-path——SPFA[J].Journal of Southwest Jiaotong University,1994,29(2):207-212.(in Chinese) [16] KITADA H,SUZUKI T,KIMURA T,et al.The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology[A].Proceedings of 2007 IEEE International Interconnect Technology Conference[C].Burlingame:IEEE,2007.10-12. |