电子学报 ›› 2012, Vol. 40 ›› Issue (5): 971-976.DOI: 10.3969/j.issn.0372-2112.2012.05.017

• 学术论文 • 上一篇    下一篇

2TF:一种协同考虑过硅通孔和热量的三维芯片布图规划算法

王伟1,3, 张欢1, 方芳2, 陈田1,3, 刘军1, 李欣3, 邹毅文1   

  1. 1. 合肥工业大学计算机与信息学院, 安徽合肥 230009;2. 合肥工业大学管理学院, 安徽合肥 230009;3. 情感计算与先进智能机器安徽省重点实验室, 安徽合肥 230009
  • 收稿日期:2011-07-20 修回日期:2011-12-22 出版日期:2012-05-25
  • 基金资助:
    国家自然科学基金(No.61106037); 博士点基金新教师项目(No.200803591033); 计算机体系结构国家重点实验室开放课题(No.CARCH201101); 合肥工业大学研究生教改项目(No.YJG2010X10); 中央高校基本科研业务费专项资金

2TF: A Collaborative Considered TSV and Thermal Floorplanning Algorithm for Three-Dimensional Chip

WANG Wei1,3, ZHANG Huan1, FANG Fang2, CHEN Tian1,3, LIU Jun1, LI Xin3, ZOU Yi-wen1   

  1. 1. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;2. School of management, Hefei University of Technology, Hefei, Anhui 230009, China;3. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei, Anhui 230009, China
  • Received:2011-07-20 Revised:2011-12-22 Online:2012-05-25 Published:2012-05-25

摘要: 三维芯片由多个平面器件层垂直堆叠而成,并通过过硅通孔(TSV,Through Silicon Via)进行层间互连,显著缩短了互连线长度、提高了芯片集成度.但三维芯片也带来了一系列问题,其中单个过硅通孔在目前的工艺尺寸下占据相对较大的芯片面积,且其相对滞后的对准技术亦降低了芯片良率,因此在三维芯片中引入过多的过硅通孔将增加芯片的制造和测试成本.垂直堆叠在使得芯片集成度急剧提高的同时也使得芯片的功耗密度在相同的面积上成倍增长,由此导致芯片发热量成倍增长.针对上述问题,本文提出了一种协同考虑过硅通孔和热量的三维芯片布图规划算法2TF,协同考虑了器件功耗、互连线功耗和过硅通孔数目.在MCNC标准电路上的实验结果表明,本文算法过硅通孔数目和芯片的峰值温度都有较大的降低.

关键词: 三维芯片, 布图规划, 过硅通孔, 热量, 互连线功耗

Abstract: Three-dimensional (3D) chip is structured by vertically stacked multi-planar device layers,which is used by TSVs (Through Silicon Vias) for vertical interconnection between different layers,so it significantly reduces the wire length and increases chip integration density.However,Series of problems are brought by three-dimensional chips.for example,a single TSV occupies a relatively larger chip area in terms of the present feature size,and the immaturity of the alignment technique of the TSVs also lowers the yield of the chip,so the introduction of too many TSVs will increase the cost of chip manufacturing and testing.Vertical stacking makes the chip integration density and the power density in the same area increase a lot simultaneously,resulting heat doubles.For these problems,we propose a collaborative considered TSV and Thermal Floorplanning (2TF) algorithm,that the device power,interconnect power and the number of TSVs are simultaneously considered.The experimental results on the MCNC benchmark circuits have shown that the number of TSVs and the peak temperature of the chip have a greater improvement.

Key words: three-dimensional chip, floorplaning, through silicon via, thermal, interconnect power

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