电子学报 ›› 2012, Vol. 40 ›› Issue (5): 983-989.DOI: 10.3969/j.issn.0372-2112.2012.05.019

• 学术论文 • 上一篇    下一篇

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

姚磊2, 蔡觉平1, 李赞2, 张海林2, 王韶力2   

  1. 1. 宽带隙半导体国家重点实验室, 陕西西安 710071;2. 西安电子科技大学综合业务网国家重点实验室, 陕西西安 710071
  • 收稿日期:2011-08-29 修回日期:2012-02-13 出版日期:2012-05-25
  • 基金资助:
    国家新一代宽带无线移动通信网科技重大专项(No.2010ZX03006-002-04); 高等学校学科创新引智计划(No.B08038); 国家自然科学基金(No.61076031,No.60832001,No.61072070)

A Fault-Tolerant Routing Algorithm Based on BIST for 2D-Mesh Network-on-Chip without Using Virtual Channels

YAO Lei2, CAI Jue-ping1, LI Zan2, ZHANG Hai-lin2, WANG Shao-Li2   

  1. 1. Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, Xi'an, Shaanxi 710071, China;2. State Key Laboratory of ISN, Xidian University, Xi'an, Shaanxi 710071, China
  • Received:2011-08-29 Revised:2012-02-13 Online:2012-05-25 Published:2012-05-25

摘要: 在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.

关键词: 容错, 片上网络, 虚通道, 内建自测

Abstract: To solve fault-tolerant problem in 2D-Mesh Network-on-Chip (NoC) with more than one fault node,a novel fault-tolerant routing algorithm without virtual channels is proposed on the basis of Zhang's algorithm.The algorithm use Built-in Self Test (BIST) mechanism to get fault nodes'location information.Then,by optimizing the fault-tolerant strategy,the traffic loads on the boundaries of fault region can be balanced and the transmission distance of the packets routing around the faults is shortened.Simulation results in 8×8 2D-Mesh NoC show that,as the change of fault block in position,the proposed algorithm can improve network injection rate by 1.2% to 4.8% compared to Chen's algorithm when the fault region is 2×2,network latency is 70 cycles.Moreover,with the increase in area of the fault region,proposed algorithm provides a better performance in reducing communication latency and increasing network throughput.

Key words: fault tolerance, network-on-chip(NoC), virtual channels, built-in self test(BIST)

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