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电子学报 ›› 2012, Vol. 40 ›› Issue (5): 1030-1033.DOI: 10.3969/j.issn.0372-2112.2012.05.027

• 科研通信 • 上一篇    下一篇

并行折叠计数器的BIST方案

梁华国1, 李鑫2, 陈田2, 王伟2, 易茂祥1   

  1. 1. 合肥工业大学电子科学与应用物理学院, 安徽合肥 23009;2. 合肥工业大学计算机与信息学院, 安徽合肥 23009
  • 收稿日期:2011-07-28 修回日期:2012-02-06 出版日期:2012-05-25
    • 基金资助:
    • 国家自然科学基金 (No.60876028); 博士点基金 (No.200803590006); 安徽高校省级自然科学研究重点项目 (No.KJ2010A280)

BIST Scheme of Parallel Folding Counters

LIANG Hua-guo1, LI Xin2, CHEN Tian2, WANG Wei2, YI Mao-xiang1   

  1. 1. School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei, Anhui 23009, China;2. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 23009, China
  • Received:2011-07-28 Revised:2012-02-06 Online:2012-05-25 Published:2012-05-25

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摘要： 本文提出了一种新的基于初始状态的并行折叠计数结构,并给出了建议的多扫描链的BIST方案.与国际上同类方法相比,该方案需要更少的测试数据存储容量、更短的测试应用时间,其平均测试应用时间是同类方案的0.265%,并且能很好地适用于传统的EDA设计流程.

关键词: 内建自测试, 线性反馈移位寄存器, 并行折叠计数器, 多扫描链, 测试数据压缩

Abstract: A new architecture of parallel folding counters is presented and a preferred BIST scheme of multiple scan chains is advised.Compared to international similar approaches,the proposed scheme needs less storage volume and shorter test application time,test application time is only as much as 0.265% of other similar scheme,and is compatible with traditional scan-based design flow.

Key words: built-in self-test (BIST), linear feedback shift registers (LFSR), parallel folding counters, multiple scan chains, test data compression

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