防御零值功耗攻击的AES SubByte模块设计及其VLSI实现

doi:10.3969/j.issn.0372-2112.2012.11.007

电子学报 ›› 2012, Vol. 40 ›› Issue (11): 2183-2187.DOI: 10.3969/j.issn.0372-2112.2012.11.007

防御零值功耗攻击的AES SubByte模块设计及其VLSI实现

汪鹏君, 郝李鹏, 张跃军

宁波大学电路与系统研究所,浙江宁波 315211

收稿日期:2011-10-20 修回日期:2012-02-28 出版日期:2012-11-25 发布日期:2012-11-25
作者简介:汪鹏君 男,1966年出生于浙江奉化,博士,教授,博士生导师,中国电子学会高级会员,中国计算机学会高级会员,中国电子学会电子线路与系统专业委员会委员,中国计算机学会多值逻辑与模糊逻辑专业委员会委员,目前主要从事多值逻辑电路和低功耗集成电路理论及设计方面的研究工作. E-mail:wangpengjun@nbu.edu.cn 郝李鹏 男,1987年出生于安徽安庆,硕士研究生,主要从事低功耗与高信息密度集成电路设计方面的研究工作. 张跃军 男,1982年出生于浙江台州,博士研究生,主要从事低功耗与高信息密度集成电路设计、防御DPA攻击VLSI设计方面的研究工作.
基金资助:
国家自然科学基金(No.61274132;No.61076032);博士点基金(No.20113305110005);浙江省重点科技创新团队项目(No.2011R09021-04);浙江省大学生科技新创活动计划(新苗人才计划)项目资助课题

Design of AES SubByte Module of Anti-Zero Value Power Attack and Its VLSI Implementation

WANG Peng-jun, HAO Li-peng, ZHANG Yue-jun

Institute of Circuits and Systems,Ningbo University,Ningbo,Zhejiang 315211,China

Received:2011-10-20 Revised:2012-02-28 Online:2012-11-25 Published:2012-11-25

摘要/Abstract

摘要： 密码器件在执行高级加密标准(Advanced Encryption Standard,AES)时常以能量消耗方式泄漏密钥信息,为有效降低其与实际处理数据之间的相关性,该文提出一种具有防御零值功耗攻击性能的AES SubByte模块设计及其VLSI实现方案.首先,在分析GF(256)域求逆算法的基础上,采用关键模块复用的方法,提出一种更为有效的加法性屏蔽求逆算法;然后依此进一步得到一种新型的SubByte模块结构,实现在不影响对所有中间数据进行加法性屏蔽编码的同时,减少电路的芯片开销、提高电路的工作速度.实验结果表明,所设计的电路具有正确的逻辑功能.与传统SubByte模块比较,该设计的最高工作频率和面积都有较大的优化.

关键词: SubByte模块, 零值功耗攻击, 差分功耗攻击, 加法性屏蔽, 高级加密标准

Abstract: The secret information of cipherware leaks as energy consumption during AES implementation.To reduce the correlation between the secret information and the processing data effectively,this paper investigate a design of AES SubByte module of anti-zero value power attack and its VLSI implementation.First,by analyzing the traditional GF(256) inversion algorithm,an improved additive masking GF(256) inversion algorithm which adopts key module reuse method is proposed.Then a novel SubByte module structure is constructed by applying such algorithm,which has significant area and speed improvement and all data can be additive masked.The experimental results show that the novel scheme has correct logic function.Compared with traditional SubByte module,a remarkable improvement is achieved by the proposed approach on highest working frequency and area.

Key words: SubByte Module, zero-value power attack, differential power analysis(DPA), additive mask, advanced encryption standard(AES)

中图分类号:

TN918.4

汪鹏君, 郝李鹏, 张跃军. 防御零值功耗攻击的AES SubByte模块设计及其VLSI实现[J]. 电子学报, 2012, 40(11): 2183-2187.

WANG Peng-jun, HAO Li-peng, ZHANG Yue-jun. Design of AES SubByte Module of Anti-Zero Value Power Attack and Its VLSI Implementation[J]. Acta Electronica Sinica, 2012, 40(11): 2183-2187.

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防御零值功耗攻击的AES SubByte模块设计及其VLSI实现

Design of AES SubByte Module of Anti-Zero Value Power Attack and Its VLSI Implementation

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