考虑时间因素的不同基本门故障概率计算

doi:10.3969/j.issn.0372-2112.2013.04.007

电子学报 ›› 2013, Vol. 41 ›› Issue (4): 666-673.DOI: 10.3969/j.issn.0372-2112.2013.04.007

考虑时间因素的不同基本门故障概率计算

肖杰, 江建慧

同济大学软件学院,上海 201804

收稿日期:2011-12-23 修回日期:2012-12-10 出版日期:2013-04-25
- 作者简介:
- 肖杰 男,1984年生,江西吉安人.同济大学计算机系统结构专业博士研究生.从事可信计算,网络可靠性等方面的研究. E-mail:xiaojiexqj@gmail.com 江建慧 男,1964年生,浙江淳安人.博士、教授、博士生导师,从事可信系统与网络、软件可靠性工程、VLSI测试与容错等方面的研究. E-mail:jhjiang@tongji.edu.cn
- 基金资助:
- 国家自然科学基金 (No.60903033); 国家973重点基础研究发展计划 (No.2005CB321604)

The Calculation of Fault Probability of Different Elementary Gates Considering Time Factor

XIAO Jie, JIANG Jian-hui

School of Software Engineering, Tongji University, Shanghai 201804, China

Received:2011-12-23 Revised:2012-12-10 Online:2013-04-25 Published:2013-04-25

摘要/Abstract

摘要： 在门级电路的可靠性概率评估方法中,基本门的故障概率p一般人为设定或以常数形式出现.考虑到不同基本门的故障概率具有随时间变化的特性并结合其输入导线,本文构建了考虑输入负载的随时间变化的不同基本门的故障概率模型.理论分析与实验结果表明,基于弱链接模型的双峰对数正态分布更适合用来表示输入导线故障概率的时间分布.用本文方法、美国军用标准MIK-HDBK-217及Monte Carlo方法计算了ISCAS85基准电路的可靠度并进行了比较,还通过了行业标准的检验,结果验证了本文所构建模型的合理性.

关键词: 时间因素, 输入负载, 输入导线, CMOS器件, 不同基本门的故障概率

Abstract: The fault probability of the elementary gate p for the reliability estimation of gate-level circuits had been given based on expert experience or as a constant generally.Considering the time change of properties of fault probability and the input-interconnects of different elementary gates,a fault probability model considering input loads and time factor is constructed.Theoretical analysis and experimental results show that the bimodal lognormal distribution based on weak link model is more suitable to describe the time distribution of the input-interconnect fault probability.The reliability values of ISCAS 85 benchmark circuits are calculated and compared by the iterative probability transfer matrix based on the proposed model,the reliability calculation method recommended by MIL-HDBK-217 standard and the reliability simulation method adopted by Monte Carlo.The industrial standard is also used to further test.It shows that the proposed model is reasonable.

Key words: time factor, input load, input-interconnect, CMOS device, the fault probability of different elementary gates

中图分类号:

TP331

肖杰, 江建慧. 考虑时间因素的不同基本门故障概率计算[J]. 电子学报, 2013, 41(4): 666-673.

XIAO Jie, JIANG Jian-hui. The Calculation of Fault Probability of Different Elementary Gates Considering Time Factor[J]. Acta Electronica Sinica, 2013, 41(4): 666-673.

参考文献

[1] 王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,37(2):24 1-247. WANG Zhen,JIANG Jian-hui.A serial method of circuit reliability calculation bas ed on probabilistic transfer matrix [J].Acta Electronica Sinica,2009,37(2):241 -247.(in Chinese)

[2] J Xiao,J-H Jiang,X-G Zhu.A method of gate-level circuit reliability estimatio n based on iterative PTM model[A].Proceeding of IEEE 17th Pacific Rim Interna tional Symposium on Dependable Computing[C].Los Alamitos:IEEE Computer Society ,2011.276-277.

[3] Han J,Hao C,Erin B.Reliability evaluation of logic circuits using probabilistic gate models[J].Microelectron Reliability,2011,51(2):468-476.

[4] 王真,江建慧.考虑版图级因素的PTM中故障感染率的计算[J].哈尔滨工业大学学报,2009,4 1(S):124-129. Wang Zhen,Jiang Jian-hui.The calculation of fault infection probability in PTM considering factors of layout[J].Journal of Harbin Institute of Technology,200 9,41(S):124-129.(in Chinese)

[5] 肖杰,江建慧.结合版图结构信息的基本门电路故障概率估计[J].电子学报,2012,40(2):23 5-240. Xiao Jie,Jiang Jian-hui.The estimation of fault probability of elementary gates based on the layout structure information[J].Acta Electronica Sinica,2012,40( 2):235-240.(in Chinese)

[6] J-X Fang,S S Sapatnekar.Scalable methods for the analysis and optimization of g ate oxide breakdown[A].Proceeding of IEEE 11th International Symposium on Qual ity Electronic Design[C].Los Alamitos:IEEE Computer Society,2010.638-645.

[7] MIL-HDBK-344A.Military handbook:Environmental stress screening of electronic e quipment[S].

[8] Liew B K,Fang P,Hu C M.Circuit reliability simulator for interconnect,via,and co ntact electromigration[J].IEEE Transactions on Electronic Devices,1992,39(11) :2472-2479.

[9] Li B Z,Christiansen C,Gill J,et al.Threshold electromigration failure time and i ts statistics for Cu interconnects[J].Journal of Applied Physics,2006,100(1145 16):1-10.

[10] Fischer A H,Abel A,Lepper M,et al.Modeling bimodal electromigration failure dist ributions[J].Microelectronics Reliability,2001,41(3):445-453.

[11] 辛维平,庄奕琪,李小明.片上栅氧化经时击穿失效监测电路与方法[J].电子学报,2012,40(11):2188-2193. Xin Wei-ping,Zhuang Yi-qi,Li Xiao-ming.An on-chip circuit for monitoring fai lure due to TDDB[J].Acta Electronica Sinica,2012,40(11):2188-2193.(in Chinese)

[12] Wu E Y,Sune J.Power law voltage acceleration:a key element for ultra-thin gate oxide reliability[J].Microelectronic Reliability,2005,45(12):1809-1834.

[13] Wu E Y,Nowak W J,Vayshenker A,et al.CMOS scaling beyond the 100-nm node with si licon-dioxide-based gate dielectrics[J].IBM Journal of Research and Developm ent,2002,46(2/3):287-298.

[14] Jong H P,Byung T A.Electromigration model for the prediction of lifetime based o n the failure unit statistics in aluminum metallization[J].Journal of Applied Physics,2003,93(2):883-892.

[1]	杨若婷, 任洁, 高小平, 王镇. 超导单磁通量子数字电路的全加器设计与应用探索[J]. 电子学报, 0, (): 1-7.
[2]	吴钰, 王伦耀, 储著飞, 夏银水. 一种功能可配置的可逆触发器设计[J]. 电子学报, 2022, 50(6): 1466-1471.
[3]	汪鹏君, 叶顺心, 张跃军, 张会红. 基于线性无关矩阵的按需解锁硬件混淆方法[J]. 电子学报, 2022, 50(3): 703-709.
[4]	吴钰, 张莹, 王伦耀, 储著飞, 夏银水. 一种可逆有限状态机的电路设计[J]. 电子学报, 2020, 48(11): 2226-2232.
[5]	马超, 戴紫彬, 李伟, 南龙梅. 基于Inverse Butterfly/Butterfly网络的置换-逆序与置换-移位选路算法[J]. 电子学报, 2017, 45(11): 2685-2694.
[6]	李冰, 周岑军, 陈帅, 吉建华. 用于SRAM PUFs的伪随机数发生器的FPGA实现[J]. 电子学报, 2017, 45(9): 2106-2112.
[7]	汪鹏君, 龚道辉, 张会红, 康耀鹏. 基于CNFET的高性能三值SRAM-PUF电路设计[J]. 电子学报, 2017, 45(5): 1090-1095.
[8]	马超, 李伟, 戴紫彬, 冯晓. 新型可重构移位-置换单元研究与设计[J]. 电子学报, 2017, 45(5): 1025-1034.
[9]	吴金, 张有志, 赵荣琦, 李超, 郑丽霞. 一种应用于TDC的低抖动延迟锁相环电路设计[J]. 电子学报, 2017, 45(2): 452-458.
[10]	卜登立, 江建慧. 基于Pareto支配的MPRM电路面积与可靠性优化[J]. 电子学报, 2016, 44(11): 2653-2659.
[11]	汪鹏君, 李刚, 钱浩宇. 可配置电阻分压型DAC-PUF电路设计[J]. 电子学报, 2016, 44(7): 1630-1635.
[12]	汪鹏君, 张学龙, 张跃军. 基于最优控制电压的高鲁棒性PUF电路设计[J]. 电子学报, 2015, 43(5): 907-910.
[13]	肖杰, 江建慧, 杨旭华, 梁家荣. 一个面向缺陷分析的电路成品率与可靠性的关系模型[J]. 电子学报, 2014, 42(4): 747-755.
[14]	肖杰;江建慧. 结合版图结构信息的基本门电路故障概率估计[J]. 电子学报, 2012, 40(2): 235-240.
[15]	高昕;赵文;叶蔚;张世琨;王立福. 一种基于时间序列的RFID供应链数据分析方法[J]. 电子学报, 2010, 38(2A): 26-32.

考虑时间因素的不同基本门故障概率计算

The Calculation of Fault Probability of Different Elementary Gates Considering Time Factor

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics