电子学报 ›› 2013, Vol. 41 ›› Issue (4): 666-673.DOI: 10.3969/j.issn.0372-2112.2013.04.007

• 学术论文 • 上一篇    下一篇

考虑时间因素的不同基本门故障概率计算

肖杰, 江建慧   

  1. 同济大学软件学院,上海 201804
  • 收稿日期:2011-12-23 修回日期:2012-12-10 出版日期:2013-04-25
    • 作者简介:
    • 肖 杰 男,1984年生,江西吉安人.同济大学计算机系统结构专业博士研究生.从事可信计算,网络可靠性等方面的研究. E-mail:xiaojiexqj@gmail.com 江建慧 男,1964年生,浙江淳安人.博士、教授、博士生导师,从事可信系统与网络、软件可靠性工程、VLSI测试与容错等方面的研究. E-mail:jhjiang@tongji.edu.cn
    • 基金资助:
    • 国家自然科学基金 (No.60903033); 国家973重点基础研究发展计划 (No.2005CB321604)

The Calculation of Fault Probability of Different Elementary Gates Considering Time Factor

XIAO Jie, JIANG Jian-hui   

  1. School of Software Engineering, Tongji University, Shanghai 201804, China
  • Received:2011-12-23 Revised:2012-12-10 Online:2013-04-25 Published:2013-04-25

摘要: 在门级电路的可靠性概率评估方法中,基本门的故障概率p一般人为设定或以常数形式出现.考虑到不同基本门的故障概率具有随时间变化的特性并结合其输入导线,本文构建了考虑输入负载的随时间变化的不同基本门的故障概率模型.理论分析与实验结果表明,基于弱链接模型的双峰对数正态分布更适合用来表示输入导线故障概率的时间分布.用本文方法、美国军用标准MIK-HDBK-217及Monte Carlo方法计算了ISCAS85基准电路的可靠度并进行了比较,还通过了行业标准的检验,结果验证了本文所构建模型的合理性.

关键词: 时间因素, 输入负载, 输入导线, CMOS器件, 不同基本门的故障概率

Abstract: The fault probability of the elementary gate p for the reliability estimation of gate-level circuits had been given based on expert experience or as a constant generally.Considering the time change of properties of fault probability and the input-interconnects of different elementary gates,a fault probability model considering input loads and time factor is constructed.Theoretical analysis and experimental results show that the bimodal lognormal distribution based on weak link model is more suitable to describe the time distribution of the input-interconnect fault probability.The reliability values of ISCAS 85 benchmark circuits are calculated and compared by the iterative probability transfer matrix based on the proposed model,the reliability calculation method recommended by MIL-HDBK-217 standard and the reliability simulation method adopted by Monte Carlo.The industrial standard is also used to further test.It shows that the proposed model is reasonable.

Key words: time factor, input load, input-interconnect, CMOS device, the fault probability of different elementary gates

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