[1]DeBenedictis E P.Will moore′s law be sufficient[A].Proceedings of the ACM/IEEE SC2004 Conference on Supercomputing[C].Pittsburgh:ACM,2005.45-56.[2]C Anshuman,C Krishnendu.Test data compression and decompression based on internal scan chains and Golomb coding[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2002,21(6):715-722.[3]欧阳一鸣,成丽丽,梁华国.一种基于变长数据块相关性统计的测试数据压缩和解压方法[J].电子学报,2008,36(2):298-302.Ouyang Yi-ming,Cheng Li-li,Lian Hua-guo.A new test data compression technique based on static relativity of variable length data block[J].Acta Electronica Sinica,2008,36(2):298-303.(in Chinese)[4]P T Gonciari,B Al-Hashimi,et al.Improving compression ratio,area overhead,and test application time for system-on-a-chip test data compression/decompression[A].Proceedings of the Conference on Design,Automation and Test in Europe[C].Paris:ACM,2002.604-611.[5]Erik Larsson,Klas Arvidsson,et al.Efficient test solutions for core-based designs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2004,23(5):758-775.[6]赵建武,师奕兵,等.复用NoC 测试IP 芯核测试存取链优化配置[J].微电子学,2009,39(6):874-878.ZHAO Jian-wu,SHI Yi-bing,et al.Optimal test access chain configuration for reusing NoC to test IP cores[J].Microelectronics,2009,39(6):874-878.(in Chinese) [7]Krishnendu Chakrabarty.Test scheduling for core-based systems using mixed-integer linear programming[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2000,19(10):1163-1174.[8]Sandeep Korann.On test scheduling for core-based SoCs[A].Proceedings of the 15th International Conference on VLSI Design[C].Baugalore:ACM,2002.505-510.[9]Gang Zeng,Hideo Ito.Concurrent core test for test cost reduction using merged test set and scan tree[A].Proceedings of the 2005 International Conference on Computer Design[C].San Jose:IEEE,2005.143-146.[10]方芳,韩银和,李晓维.热量敏感的众核芯片多播并行测试方法[J].计算机辅助设计与图形学报,2010,22(5):845-851.FANG Fang,HAN Yin-he,LI Xiao-wei.A thermal-aware parallel multicast tesing method based on many-core chips[J].Journal of Computer-Aided Design & Computer Graphics,2010,22(5):845-851.(in Chinese)[11]M Alexandre.Amory Frederico Ferlini,et al.DfT for the reuse of networks-on-chip as test access mechanism[A].Proceedings of the 25th IEEE VLSI Test Symposium[C].Berkeley:IEEE,2007.435-440.[12]Vikram Iyengart,Krishnendu Chakrabartyt,et al.Test wrapper and test access mechanism co-optimization for system-on-chip[A].Proceedings of International Test Conference[C].Baltimore:ACM,2001.1023-1032.[13]C Liu,V Iyengar,J Shi,et al.Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking[A].Proceedings of IEEE VLSI Test Symposium[C].Palm Springs:IEEE,2005.349-354.[14]Jia LI,Qiang XU,Yu HU,Xiaowei LI.Channel width utilization improvement in testing NoC-based systems for test time reduction[A].Proceedings of 4th IEEE International Symposium on Electronic Design,Test and Applications[C].Hong Kong:IEEE,2008.26-31. |