基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现

doi:10.3969/j.issn.0372-2112.2014.07.023

电子学报 ›› 2014, Vol. 42 ›› Issue (7): 1392-1397.DOI: 10.3969/j.issn.0372-2112.2014.07.023

基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现

祁艳杰, 刘章发

北京交通大学电子信息工程学院, 北京 100044

收稿日期:2013-04-09 修回日期:2013-07-06 出版日期:2014-07-25
- 作者简介:
- 祁艳杰 女，1987年12月出生于河北廊坊.北京交通大学硕士研究生，研究方向为verilog数字VLSI设计及FPGA嵌入式开发在射频通信方面的应用.E-mail：qiy_77@126.com；刘章发 男，汉族，1963年11月出生于安徽省.博士，现为北京交通大学电子信息工程学院教授，研究方向：通信与导航集成电路设计.E-mail：zhfliu@bjtu.edu.cn

FPGA Implementation of High Speed and High Precision Direct Digital Frequency Synthesizer Based on Parallel_CORDIC

QI Yan-jie, LIU Zhang-fa

School of Electronic and Information Engineering, Beijing Jiaotong University, Beijing 100044, China

Received:2013-04-09 Revised:2013-07-06 Online:2014-07-25 Published:2014-07-25

摘要/Abstract

摘要：

本文提出了一种直接数字频率合成器（DDFS）的设计，以Parallel_CORDIC（COrdinate Rotation Digital Computer）算法模块替代传统的查找表方式，实现了相位与幅度的一一对应，输出相位完全正交的正余弦波形；同时应用旋转角度预测及4：2的进位保存加法器（CSA）技术，将速度比传统CORDIC算法提高41.7%，精度提高到10^-4.最后以Xilinx的FPGA硬件实现整个设计.

关键词: 直接数字频率合成技术(DDFS), ParallelCORDIC, 进位保存加法器(CSA), FPGA

Abstract:

The design of a direct digital frequency synthesizer (DDFS) is proposed in this paper.Parallel_CORDIC (Cordinate Rotation Digital Computer) algorithm module is used to replace the traditional look-up table method,the phase and amplitude of a one-to-one correspondence is realized,and outputs are sine and cosine waveforms that completely orthogonal in phase.The angle prediction and 4:2 Carry Save Adder (CSA) technologies are also applied in the design,the calculation speed is 41.7% faster than the traditional CORDIC algorithm and the accuracy is improved to 10^-4.Finally,the whole design is implemented based on Xilinx FPGA development board.

Key words: direct digital frequency synthesis (DDFS), Parallel CORDIC, Carry Save Adder (CSA), FPGA

中图分类号:

TN911.23

祁艳杰, 刘章发. 基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现[J]. 电子学报, 2014, 42(7): 1392-1397.

QI Yan-jie, LIU Zhang-fa. FPGA Implementation of High Speed and High Precision Direct Digital Frequency Synthesizer Based on Parallel_CORDIC[J]. Acta Electronica Sinica, 2014, 42(7): 1392-1397.

参考文献

[1] Avanindra Madisetti,Alan Y Kwentus,Alan N Willson.A 100-MHz,16-b,drectdigital frequency synthesizer with a 100-dBc spurious-free dynamic range[J].IEEE Journal of Solid-State Circuits,1999,34(8):1034-1043.
[2] Chang Yongkang,Earl E Swartzlander.An analysis of the CORDIC algorithm for direct digital frequency synthesis[A].Proceedings of the IEEE International Conference on Application-Specific Systems,Architectures and Processors[C].NY,USA:IEEE,2002.112-119.
[3] TerenceK Rodrigues,Earl E Swartzlander.Adaptive CORDIC:using parallel angle recoding to accelerate rotations[J].IEEE Computer Society,2010,59(4):522-531.
[4] 张晓彤,辛茹,王沁,李涵.基于改进混合式CORDIC算法的直接数字频率合成器设计[J].电子学报,2008,36(6):1144-1148. ZHANG Xiao-tong,XINRu,WANG Qin,LI Han.Design of direct digital frequency synthesizer based on improved hybrid CORDIC algorithm[J].Acta Electronica Sinica,2008,36(6):1144-1148.(in Chinese)
[5] Shen-Fu Hsiao,Yu-Hen Hu,Tso-Bing Juang.A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations[J].IEEE Signal Processing Letters 2004,11(2):152-155.
[6] Tso-Pin Chuang,Chao-Chuan Huang,Shen-Fu Hsiao.Design of a CORDIC-based SIN/COS intellectual property (IP) using predictable sign bits[A].Proceedings of the 27th European Solid-State Circuits Conference[C].Villach,Austria,2001.277-280.
[7] B Lakshmi,A S Dhar.FPGA implementation of a high speed VLSI architecture for CORDIC[A].Proceedings of IEEE Region 10 Conference TENCON[C].USA:IEEE,2009.1-5.
[8] Tso-Bing Juang.Low latencyangle recoding methods for the higher bit-width parallel CORDIC rotator implementations[J].IEEE Circuits and Systems Society,2008,55(11):1139-1143.
[9] Tso-Bing Juang,Shen-Fu Hsiao,Ming-Yu Tsai.Para-CORDIC:parallel CORDIC rotation algorithm[J].IEEE Circuits and Systems Society,2004,51(8):1515-1524.
[10] Hu,Yu Hen.The quantization effects of the CORDIC algorithm[J].IEEE Signal Processing Society,1992,40(4):834-844.
[11] Chip-Hong Chang,Jiangmin Gu,Mingyan Zhang.Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits[J].IEEE Transactions on Circuits and Systems,2004,51(10):1985-1997.
[12] Karuna Prasad,Keshab K Parhi.Low-power 4-2 and 5-2 compressors[A].Conference Record of the Thirty-Fifth Asilomar Conference on Signals,Systems and Computers[C].USA:IEEE,2001,1:129-133.
[13] Alvaro Vàzquez,Elisardo Antelo.Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree[A].Conference Record of the Forty Fourth Asilomar Conference on Signals,Systems and Computers (ASILOMAR)[C].USA:IEEE,2010.1685-1689.
[14] Junhyung Um,Taewhan Kim.An optimal allocation of carry-save-adders in arithmetic circuits[J].IEEE Transactions on Computers,2001,50(3):215-232.
[15] Anita Sharma,Dr R DDaruwala.Digital frequency (sinusoidal) synthesizer using CORDIC algorithm[A].Proceedings of IEEE 3rd International Conference on Communication Software and Networks (ICCSN)[C].USA:IEEE,2011.521-524.

基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现

FPGA Implementation of High Speed and High Precision Direct Digital Frequency Synthesizer Based on Parallel_CORDIC

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

[1]	袁海英, 曾智勇, 成君鹏. 面向灵活并行度的稀疏卷积神经网络加速器[J]. 电子学报, 2022, 50(8): 1811-1818.
[2]	陈晓杰, 李斌, 周清雷. RTL级可扩展高性能数据压缩方法实现[J]. 电子学报, 2022, 50(7): 1548-1557.
[3]	许皓文, 陆浩, 王振占. 高光谱微波辐射计系统中2GHz带宽数字谱仪设计[J]. 电子学报, 2022, 50(6): 1472-1479.
[4]	曲立国, 陈国豪, 胡俊, 陈鹏. 单次扫描连通域分析算法研究综述[J]. 电子学报, 2022, 50(6): 1521-1536.
[5]	王鹏, 邹彬, 刘金枝, 周丹阳. 基于Xilinx型FPGA系统单粒子效应评估方法研究[J]. 电子学报, 2022, 50(11): 2716-2721.
[6]	李斌, 齐延荣, 周清雷. 基于Winograd算法的目标检测加速器设计与优化[J]. 电子学报, 2022, 50(10): 2387-2397.
[7]	蔡莹, 朱翔, 王舰, 李昊远, 韩建伟. 基于激光注入的FPGA加密防护设计验证研究[J]. 电子学报, 2022, 50(10): 2381-2386.
[8]	张建民, 黎铁军, 马柯帆, 肖立权. 一种加速FPGA布线的不可满足子式求解算法[J]. 电子学报, 2021, 49(6): 1210-1216.
[9]	刘杰, 葛一凡, 田明, 马力强. 基于ZYNQ的可重构卷积神经网络加速器[J]. 电子学报, 2021, 49(4): 729-735.
[10]	孙明乾, 乔庐峰, 陈庆华. 一种无匹配时间损耗的DFA压缩算法的研究与实现[J]. 电子学报, 2020, 48(6): 1132-1139.
[11]	蹇强, 张培勇, 王雪洁. 一种可配置的CNN协加速器的FPGA实现方法[J]. 电子学报, 2019, 47(7): 1525-1531.
[12]	刘公绪, 史凌峰, 辛东金. 基于FPGA的零误差大数阶乘算法的设计与实现[J]. 电子学报, 2019, 47(5): 1180-1184.
[13]	余乐, 李任伟, 王瑶, 李洋洋, 吴超, 贾瑞. 综述:面向SoC-FPGA的开源处理器[J]. 电子学报, 2018, 46(4): 992-1004.
[14]	薛一鸣, 陈鹞, 何宁宁, 胡彩娥, 王建平. 基于DFT滤波器组的低时延FPGA语音处理实现研究[J]. 电子学报, 2018, 46(3): 695-701.
[15]	孙悦, 王传伟, 康龙飞, 叶超, 张信. 基于CORDIC的精确快速幅相解算方法[J]. 电子学报, 2018, 46(12): 2978-2984.