电子学报 ›› 2014, Vol. 42 ›› Issue (7): 1392-1397.DOI: 10.3969/j.issn.0372-2112.2014.07.023

• 科研通信 • 上一篇    下一篇

基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现

祁艳杰, 刘章发   

  1. 北京交通大学电子信息工程学院, 北京 100044
  • 收稿日期:2013-04-09 修回日期:2013-07-06 出版日期:2014-07-25
    • 作者简介:
    • 祁艳杰 女,1987年12月出生于河北廊坊.北京交通大学硕士研究生,研究方向为verilog数字VLSI设计及FPGA嵌入式开发在射频通信方面的应用.E-mail:qiy_77@126.com;刘章发 男,汉族,1963年11月出生于安徽省.博士,现为北京交通大学电子信息工程学院教授,研究方向:通信与导航集成电路设计.E-mail:zhfliu@bjtu.edu.cn

FPGA Implementation of High Speed and High Precision Direct Digital Frequency Synthesizer Based on Parallel_CORDIC

QI Yan-jie, LIU Zhang-fa   

  1. School of Electronic and Information Engineering, Beijing Jiaotong University, Beijing 100044, China
  • Received:2013-04-09 Revised:2013-07-06 Online:2014-07-25 Published:2014-07-25

摘要:

本文提出了一种直接数字频率合成器(DDFS)的设计,以Parallel_CORDIC(COrdinate Rotation Digital Computer)算法模块替代传统的查找表方式,实现了相位与幅度的一一对应,输出相位完全正交的正余弦波形;同时应用旋转角度预测及4:2的进位保存加法器(CSA)技术,将速度比传统CORDIC算法提高41.7%,精度提高到10-4.最后以Xilinx的FPGA硬件实现整个设计.

关键词: 直接数字频率合成技术(DDFS), ParallelCORDIC, 进位保存加法器(CSA), FPGA

Abstract:

The design of a direct digital frequency synthesizer (DDFS) is proposed in this paper.Parallel_CORDIC (Cordinate Rotation Digital Computer) algorithm module is used to replace the traditional look-up table method,the phase and amplitude of a one-to-one correspondence is realized,and outputs are sine and cosine waveforms that completely orthogonal in phase.The angle prediction and 4:2 Carry Save Adder (CSA) technologies are also applied in the design,the calculation speed is 41.7% faster than the traditional CORDIC algorithm and the accuracy is improved to 10-4.Finally,the whole design is implemented based on Xilinx FPGA development board.

Key words: direct digital frequency synthesis (DDFS), Parallel CORDIC, Carry Save Adder (CSA), FPGA

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