UM-BUS总线及接入式体系结构

doi:10.3969/j.issn.0372-2112.2015.09.015

电子学报 ›› 2015, Vol. 43 ›› Issue (9): 1776-1785.DOI: 10.3969/j.issn.0372-2112.2015.09.015

UM-BUS总线及接入式体系结构

张伟功^1,2, 周继芹², 李杰³, 王晶^1,2, 丁瑞¹, 邓哲⁴, 王嘉佳⁴, 杜瑞⁴

1. 首都师范大学信息工程学院, 北京 100048;
2. 北京数学与信息交叉科学 2011协同创新中心, 北京 100048;
3. 山东航天电子技术研究所, 山东烟台 264003;
4. 北京市高可靠嵌入式系统工程技术研究中心, 北京 100048

收稿日期:2014-07-17 修回日期:2014-10-20 出版日期:2015-09-25
- 作者简介:
- 张伟功 男,1967年生于山西临猗.首都师范大学信息工程学院研究员、博士生导师.主要研究方向为高可靠嵌入式计算机体系结构与应用技术.E-mail:zwg771@cnu.edu.cn;周继芹 女,1978年生于山东安丘.首都师范大学数学科学学院博士生.主要研究方向为计算机系统体系结构与性能评价.
- 基金资助:
- 国家自然科学基金 (No.61170009); 北京市自然科学基金 (No.4132016); 北京市属高等学校创新团队建设与教师职业发展计划; 北京市教委科技基地建设项目

UM-BUS and a Plug and Play Architecture

ZHANG Wei-gong^1,2, ZHOU Ji-qin², LI Jie³, WANG Jing^1,2, DING Rui¹, DENG Zhe⁴, WANG Jia-jia⁴, DU Rui⁴

1. College of Information Engineering, Capital Normal University, Beijing 100048, China;
2. Beijing Center for Mathematics and Information Interdisciplinary Sciences, Beijing 100048, China;
3. Shandong Aerospace Electro-technology Institute, Yantai, Shandong 264003, China;
4. Beijing Engineering Research Center of High Reliable Embedded System, Beijing 100048, China

Received:2014-07-17 Revised:2014-10-20 Online:2015-09-25 Published:2015-09-25
- Supported by:
- National Natural Science Foundation of China (No.61170009); Natural Sciecne Foundation of Beijing Municipality, China (No.4132016); Innovation Team Construction Project and Teacher Career Development Program of Beijing Municipal Universities; Base Construction Project of Science and Technology Project of Beijing Municipal Education Commission

摘要/Abstract

摘要：

本文针对航天航空等领域综合电子系统在小型化、一体化设计及信息综合利用等方面的需求,提出一种可动态重构的高速串行通信总线(UM-BUS),采用N(≤32)通道并发传输,通信速率可达6.4Gbps,采用总线型拓扑结构,最大通信距离40m,支持最多30个节点直接互连,具有远程存储访问能力,采用命令应答式协议提供QoS与实时性保证;通过并发通道相互冗余与动态重构,在允许50%性能降低的情况下,能够对N/2通道故障动态容错.在UM-BUS总线基础上,本文提出一种新型的"接入式"体系结构模型,在不改变系统逻辑结构的前提下,能够突破机箱结构限制,将逻辑功能分散嵌入到控制测量对象内部,实现功能模块"接入即用",使得综合电子系统一体化设计成为可能.

关键词: 综合电子系统, 冗余容错, 高速总线, 动态重构, "接入式"体系结构, UM-BUS

Abstract:

According to the demands of miniaturization,integrated design and comprehensive information utilization for integrated electronic system in aviation and aerospace field,this paper presents the UM-BUS.It is a high-speed,dynamic reconfigurable serial bus with N(≤32) concurrent lanes of mutual redundant structure available,and the maximum communication rate of 6.4Gbps.UM-BUS is formed by general bus-topology structure where up to 30 nodes can be connected directly to provide the capability of remote memory accessing with maximum communication distance of up to 40m.UM-BUS uses command/response protocol to attain QoS and real-time guarantee.In the case of allowing 50% reduced performance,any fault in N/2 lanes can be tolerant by reconfiguring the mutual redundant concurrent lanes automatically.On the basis of UM-BUS,this paper put forward a new architecture of embedded systems.This access type architecture is geared to the needs of embedded system control and measurement applications.It does not change the logic architecture of embedded system,but this access architecture can break the structural constraints of embedded systems' chassis.It can accomplish a plug and play of the functional module by means of dispersing the logic functions to the interior of the control measurement object.By using this architecture,the integration designing of integrated electronic systems is possible to complete.

Key words: integrated electronic system, fault tolerance, high-speed bus, dynamic reconfiguration, plug and play architecture, UM-BUS

中图分类号:

TP302.8

张伟功, 周继芹, 李杰, 等. UM-BUS总线及接入式体系结构[J]. 电子学报, 2015, 43(9): 1776-1785.

ZHANG Wei-gong, ZHOU Ji-qin, LI Jie, et al. UM-BUS and a Plug and Play Architecture[J]. Acta Electronica Sinica, 2015, 43(9): 1776-1785.

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UM-BUS总线及接入式体系结构

UM-BUS and a Plug and Play Architecture

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