电子学报 ›› 2016, Vol. 44 ›› Issue (11): 2653-2659.DOI: 10.3969/j.issn.0372-2112.2016.11.013

• 学术论文 • 上一篇    下一篇

基于Pareto支配的MPRM电路面积与可靠性优化

卜登立1,2,3, 江建慧2   

  1. 1. 井冈山大学电子与信息工程学院, 江西吉安 343009;
    2. 同济大学软件学院, 上海 201804;
    3. 流域生态与地理环境检测国家测绘地理信息局重点实验室, 江西吉安 343009
  • 收稿日期:2015-05-05 修回日期:2015-10-28 出版日期:2016-11-25
    • 作者简介:
    • 卜登立,男,1975年出生,河北定州人.博士,副教授.主要研究领域为VLSI设计和可靠性评估、计算机辅助设计.E-mail:bodengli@163.com;江建慧,男,1964年出生,浙江淳安人.博士,教授,博士生导师,CCF高级会员.主要研究领域为可信系统与网络、软件可靠性工程、VLSI/SoC测试与容错.E-mail:jhjiang@tongji.edu.cn
    • 基金资助:
    • 国家自然科学基金 (No.61432017); 流域生态与地理环境监测国家测绘地理信息局重点实验室资助课题 (No.WE2016012); 吉安市科技局指导性科技计划 (吉市科计字[2016]4-4)

Pareto Dominance Based Area and Reliability Optimization of MPRM Circuits

BU Deng-li1,2,3, JIANG Jian-hui2   

  1. 1. School of Electronics and Information Engineering, Jinggangshan University, Ji'an, Jiangxi 343009, China;
    2. School of Software Engineering, Tongji University, Shanghai 201804, China;
    3. Key Laboratory of Watershed Ecology and Geographical Environment Monitoring NASG, Ji'an, Jiangxi 343009, China
  • Received:2015-05-05 Revised:2015-10-28 Online:2016-11-25 Published:2016-11-25

摘要:

针对MPRM(Mixed-Polarity Reed-Muller)电路的面积与可靠性折中优化问题,在逻辑级建立面积估算模型以及电路SER(Soft Error Rate)解析评价模型,并采用Pareto支配概念对MPRM电路进行面积与可靠性多目标优化.通过对MPRM电路的XOR部分进行树形异或门分解,并考虑多个输出之间异或门的共享,建立面积估算模型.采用信号概率和故障传播方法,并考虑电路中的逻辑屏蔽因素以及信号相关性,建立电路SER解析评价模型.根据所提出的面积和SER评价模型,采用极性向量的格雷码序穷举搜索MPRM的极性空间得到MPRM电路面积与可靠性的Pareto最优解集,并使用效率因子技术指标选取最终解.MCNC基准电路的实验结果表明,与面积最小MPRM电路相比,所选取的MPRM电路可以在较小面积开销的前提下获得较高电路可靠性.

关键词: MPRM电路, 可靠性优化, 面积优化, SER解析评价模型, Pareto支配, 多目标优化

Abstract:

Area and SER (Soft Error Rate) evaluation models at logic level are proposed for area and reliability optimization of MPRM (Mixed-Polarity Reed-Muller) circuits,the trade-off between area and reliability is achieved by using Pareto dominance based multiobjective optimization.The area is computed by decomposing the XOR part of MPRM circuit as trees of XOR gates and counting in XOR gate sharing among multiple outputs.The SER is computed by using signal probability and fault propagation techniques,and taking into account the logic masking effects and correlations among signals in the circuit network.Based on the proposed area and SER evaluation models,the Pareto optimal set for area and SER of MPRM circuit is obtained by using polarity optimization method with Gray code based exhaustive search strategy,the final solution is selected by using a metric called efficiency factor.Experimental results by using a set of benchmark circuits from MCNC show that,in comparison with the MPRM circuits with minimized area,the selected MPRM circuits have improved reliability with less area overhead.

Key words: MPRM circuits, reliability optimization, area optimization, analytical SER evaluation model, Pareto dominance, multiobjective optimization

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