基于Pareto支配的MPRM电路面积与可靠性优化

doi:10.3969/j.issn.0372-2112.2016.11.013

电子学报 ›› 2016, Vol. 44 ›› Issue (11): 2653-2659.DOI: 10.3969/j.issn.0372-2112.2016.11.013

基于Pareto支配的MPRM电路面积与可靠性优化

卜登立^1,2,3, 江建慧²

1. 井冈山大学电子与信息工程学院, 江西吉安 343009;
2. 同济大学软件学院, 上海 201804;
3. 流域生态与地理环境检测国家测绘地理信息局重点实验室, 江西吉安 343009

收稿日期:2015-05-05 修回日期:2015-10-28 出版日期:2016-11-25
- 作者简介:
- 卜登立,男,1975年出生,河北定州人.博士,副教授.主要研究领域为VLSI设计和可靠性评估、计算机辅助设计.E-mail:bodengli@163.com;江建慧,男,1964年出生,浙江淳安人.博士,教授,博士生导师,CCF高级会员.主要研究领域为可信系统与网络、软件可靠性工程、VLSI/SoC测试与容错.E-mail:jhjiang@tongji.edu.cn
- 基金资助:
- 国家自然科学基金 (No.61432017）; 流域生态与地理环境监测国家测绘地理信息局重点实验室资助课题 (No.WE2016012）; 吉安市科技局指导性科技计划 (吉市科计字[2016]4-4）

Pareto Dominance Based Area and Reliability Optimization of MPRM Circuits

BU Deng-li^1,2,3, JIANG Jian-hui²

1. School of Electronics and Information Engineering, Jinggangshan University, Ji'an, Jiangxi 343009, China;
2. School of Software Engineering, Tongji University, Shanghai 201804, China;
3. Key Laboratory of Watershed Ecology and Geographical Environment Monitoring NASG, Ji'an, Jiangxi 343009, China

Received:2015-05-05 Revised:2015-10-28 Online:2016-11-25 Published:2016-11-25

摘要/Abstract

摘要：

针对MPRM（Mixed-Polarity Reed-Muller）电路的面积与可靠性折中优化问题，在逻辑级建立面积估算模型以及电路SER（Soft Error Rate）解析评价模型，并采用Pareto支配概念对MPRM电路进行面积与可靠性多目标优化.通过对MPRM电路的XOR部分进行树形异或门分解，并考虑多个输出之间异或门的共享，建立面积估算模型.采用信号概率和故障传播方法，并考虑电路中的逻辑屏蔽因素以及信号相关性，建立电路SER解析评价模型.根据所提出的面积和SER评价模型，采用极性向量的格雷码序穷举搜索MPRM的极性空间得到MPRM电路面积与可靠性的Pareto最优解集，并使用效率因子技术指标选取最终解.MCNC基准电路的实验结果表明，与面积最小MPRM电路相比，所选取的MPRM电路可以在较小面积开销的前提下获得较高电路可靠性.

关键词: MPRM电路, 可靠性优化, 面积优化, SER解析评价模型, Pareto支配, 多目标优化

Abstract:

Area and SER (Soft Error Rate) evaluation models at logic level are proposed for area and reliability optimization of MPRM (Mixed-Polarity Reed-Muller) circuits,the trade-off between area and reliability is achieved by using Pareto dominance based multiobjective optimization.The area is computed by decomposing the XOR part of MPRM circuit as trees of XOR gates and counting in XOR gate sharing among multiple outputs.The SER is computed by using signal probability and fault propagation techniques,and taking into account the logic masking effects and correlations among signals in the circuit network.Based on the proposed area and SER evaluation models,the Pareto optimal set for area and SER of MPRM circuit is obtained by using polarity optimization method with Gray code based exhaustive search strategy,the final solution is selected by using a metric called efficiency factor.Experimental results by using a set of benchmark circuits from MCNC show that,in comparison with the MPRM circuits with minimized area,the selected MPRM circuits have improved reliability with less area overhead.

Key words: MPRM circuits, reliability optimization, area optimization, analytical SER evaluation model, Pareto dominance, multiobjective optimization

中图分类号:

卜登立, 江建慧. 基于Pareto支配的MPRM电路面积与可靠性优化[J]. 电子学报, 2016, 44(11): 2653-2659.

BU Deng-li, JIANG Jian-hui. Pareto Dominance Based Area and Reliability Optimization of MPRM Circuits[J]. Acta Electronica Sinica, 2016, 44(11): 2653-2659.

参考文献

[1] Rao W,Yang C,Karri R,et al.Toward future systems with nanoscale devices:overcoming the reliability challenge[J].Computer,2011,44(2):46-53.
[2] Luckenbill S,Lee J-Y,Hu Y,et al.RALF:reliability analysis for logic faults-an exact algorithm and its applications[A].Proceedings of the 2010 Design,Automation & Test in Europe Conference & Exhibition[C].IEEE,2010.783-788.
[3] Al-Jassani B A,Urquhart N,Almaini A E A.Manipulation and optimisation techniques for Boolean logic[J].IET Computers and Digital Techniques,2010,4(3):227-239.
[4] 汪鹏君,李辉,吴文晋,等.量子遗传算法在多输出Reed-Muller逻辑电路最佳极性搜索中的应用[J].电子学报,2010,38(5):1058-1063. Wang P J,Li H,Wu W J,et al.Application of quantum genetic algorithm in searching for best polarity of multi-output Reed-Muller logic circuits[J].Acta Electronica Sinica,2010,38(5):1058-1063.(in Chinese)
[5] 卜登立,江建慧.基于对偶逻辑的混合极性RM电路极性转换和优化方法[J].电子学报,2015,43(1):79-85. Bu D L,Jiang J H.Dual logic based polarity conversion and optimization of mixed polarity RM circuits[J].Acta Electronica Sinica,2015,43(1):79-85.(in Chinese)
[6] 汪鹏君,汪迪生,蒋志迪,等.基于PSGA算法的ISFPRM电路面积与功耗优化[J].电子学报,2013,41(8):1542-1548. Wang P J,Wang D S,Jiang Z D,et al.Area and power optimization of ISFPRM circuits based on PSGA algorithm[J].Acta Electronica Sinica,2013,41(8):1542-1548.(in Chinese)
[7] Jiang Z,Wang Z,Wang P.Delay-area trade-off for MPRM circuits based on hybrid discrete particle swarm optimization[J].Journal of Semiconductors,2013,34(6):132-137.
[8] Rahaman H,Das D K,Bhattacharya B B.Testable design of AND-EXOR logic networks with universal test sets[J].Computers and Electrical Engineering,2009,35(5):644-658.
[9] Limbrick D B,Yue S.Impact of synthesis constraints on error propagation probability of digital circuits[A].Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems[C].IEEE,2011.103-111.
[10] Chinchuluun A,Pardalos P M.A survey of recent developments in multiobjective optimization[J].Annual Operational Research,2007,154:29-50.
[11] Parker K P,Mccluskey E J.Probabilistic treatment of general combinational networks[J].IEEE Transactions on Computers,1975,C-24(6):668-670.
[12] Drechsler R,Becker B.Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1998,17(10):965-973.
[13] Ben-Jamaa M H,Mohanram K,De-Micheli G.An efficient gate library for ambipolar CNTFET logic[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2011,30(2):242-255.
[14] Krishnaswamy S,Plaza S M,Markov I L,et al.Signature-based SER analysis and design of logic circuits[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2009,28(1):74-86.
[15] Polian I,Hayes J P,Reddy S M,et al.Modeling and mitigating transient errors in logic circuits[J].IEEE Transactions on Dependable and Secure Computing,2011,8(4):537-547.
[16] Takata T,Matsunaga Y.A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits[A].Proceedings of the 17th International on-Line Testing Symposium[C].IEEE,2011.246-251.

基于Pareto支配的MPRM电路面积与可靠性优化

Pareto Dominance Based Area and Reliability Optimization of MPRM Circuits

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

[1]	钟沛龙, 黎明, 何超, 陈昊. 基于SOM聚类和自适应算子选择的高维多目标进化算法[J]. 电子学报, 2022, 50(8): 1959-1974.
[2]	魏振春, 傅宇, 马仲军, 吕增威, 石雷, 张本宏. 带时间窗的无线可充电传感器网络多目标路径规划算法[J]. 电子学报, 2022, 50(8): 1819-1829.
[3]	汪禹宏, 张屹. 基于适应度指导交配限制策略的重组算子与多目标优化研究[J]. 电子学报, 2022, 50(3): 710-717.
[4]	张屹, 陆逸舟, 王帅, 陆曈曈. 基于多源交配选择策略的重组算子与多目标优化研究[J]. 电子学报, 2021, 49(9): 1754-1760.
[5]	王蔚龙, 李勇军, 赵尚弘, 辛宁, 赵海燕, 张泰江. 基于两阶段帕累托优化的卫星下行链路功率分配方法[J]. 电子学报, 2021, 49(6): 1101-1107.
[6]	罗智勇, 朱梓豪, 谢志强, 孙广路. 面向云计算的花朵差分授粉工作流多目标优化算法研究[J]. 电子学报, 2021, 49(3): 470-476.
[7]	王亚良, 倪晨迪, 金寿松. 基于多邻居结构的自适应元胞差分算法[J]. 电子学报, 2021, 49(3): 578-585.
[8]	张磊, 刘庆, 杨尚尚, 杨海鹏, 程凡, 马海平. 基于双编码的重叠社团检测多目标优化方法[J]. 电子学报, 2021, 49(11): 2101-2107.
[9]	崔玉亚, 张德干, 张婷, 杨鹏, 朱浩丽. 一种面向移动边缘计算的多用户细粒度任务卸载调度方法[J]. 电子学报, 2021, 49(11): 2202-2207.
[10]	刘冰洁, 毕晓君. 一种基于角度信息的约束高维多目标进化算法[J]. 电子学报, 2021, 49(11): 2208-2216.
[11]	王海东, 刘云敬, 康琳, 武迎春. 射频能量捕获传感网移动能量源的布置策略研究[J]. 电子学报, 2020, 48(12): 2367-2375.
[12]	黎明, 黄珊, 陈昊, 李军华. 基于类圆映射的高维多目标可视化方法[J]. 电子学报, 2019, 47(6): 1185-1193.
[13]	谢承旺, 张飞龙, 陆建波, 肖驰, 龙广林. 一种多策略协同的多目标萤火虫算法[J]. 电子学报, 2019, 47(11): 2359-2367.
[14]	张磊, 毕晓君, 王艳娇. 基于重新匹配策略的ε约束多目标分解优化算法[J]. 电子学报, 2018, 46(5): 1032-1040.
[15]	卜登立. 基于概率表达式的MPRM电路功耗计算方法[J]. 电子学报, 2018, 46(12): 3060-3067.