电子学报 ›› 2016, Vol. 44 ›› Issue (8): 1956-1961.DOI: 10.3969/j.issn.0372-2112.2016.08.026

• 学术论文 • 上一篇    下一篇

面向类仿射型数组下标应用的参数化并行存储结构模板

郭振华, 吴艳霞, 张国印, 戴葵   

  1. 哈尔滨工程大学计算机科学与技术学院, 黑龙江哈尔滨 150001
  • 收稿日期:2014-12-01 修回日期:2015-03-10 出版日期:2016-08-25 发布日期:2016-08-25
  • 通讯作者: 吴艳霞
  • 作者简介:郭振华 男,1988年生于河北省,2010年获哈尔滨工程大学学士学位,现为哈尔滨工程大学计算机科学与技术学院博士研究生.主要研究方向为计算机体系结构、可重构编译、信息安全.E-mail:hrbeu.guozhenhua@gmail.com
  • 基金资助:
    国家自然科学基金(No.61003036);计算机体系结构国家重点实验室开放课题(No.CARCH201301);博士后科研启动基金(No.LBH-Q12134);中央高校基本科研业务经费专项基金(No.HEUCF100606)

A Parameterized Parallelism Memory Template for Affine Array Subscript Application

GUO Zhen-hua, WU Yan-xia, ZHANG Guo-yin, DAI Kui   

  1. College of Computer Science and Technology, Harbin Engineering University, Harbin, Heilongjiang 150001, China
  • Received:2014-12-01 Revised:2015-03-10 Online:2016-08-25 Published:2016-08-25

摘要: 为了解决目前可重构编译技术在为类仿射型数组下标应用生成循环流水阵列时,生成的存储系统对数据并行与重用支持不完善的问题,本文提出了一种参数化并行存储结构模板.此模板采用模块化设计思想,根据数据访存特征生成由多体交叉并行存储子模块、单体串行存储子模块、RAW Buffer缓存子模块及Smart Buffer缓存子模块构成的存储结构.为灵活生成存储结构及充分挖掘数据的并行性和重用性,本文采用访存数据依赖图方法计算存储模板的参数值.和相关工作相比,根据本文提出的存储结构模板生成的硬件,可以在占用较少的硬件资源情况下,获得较高的硬件执行速度.

关键词: 类仿射数组下标, 可重构编译, 存储结构, 数据重用, 模板

Abstract: In current reconfigurable compiling approach for solving affine subscript operations,the automatic generated feeding memory system is not optimal,especially to support an iteration pipeline structure.This paper presents a parameterized parallel memory template to mine parallelism and reusability of data,which is considered to address the lack of such aspect in reconfigurable compilers at hand.According to the analysis of characteristics of data access to affine subscript arrays in pipeline iteration,our template configures alternative sub-structures such as parallel multi-bank memory,sequential access memory,RAW Buffer and Smart Buffer.Furthermore,in phase of calculating parameter values to fill the template,the memory data dependence graph method is used,in which approach the flexibility of way to create memory structure is kept.The experimental result shows that compared with related works,the compiler can generate reconfigurable hardware performing a higher execution speed with less resources usage by employ the proposed memory template.

Key words: affine array subscript, compiler for reconfigurable computing, memory architecture, data reuse, template

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