电子学报 ›› 2016, Vol. 44 ›› Issue (12): 3011-3019.DOI: 10.3969/j.issn.0372-2112.2016.12.028

• 学术论文 • 上一篇    下一篇

考虑多时钟周期瞬态脉冲叠加的锁存窗屏蔽模型

闫爱斌1,2, 梁华国3, 黄正峰3, 蒋翠云4, 易茂祥3   

  1. 1. 合肥工业大学计算机与信息学院, 安徽合肥 230009;
    2. 安徽大学计算机科学与技术学院, 安徽合肥 230601;
    3. 合肥工业大学电子科学与应用物理学院, 安徽合肥 230009;
    4. 合肥工业大学数学学院, 安徽合肥 230009
  • 收稿日期:2015-01-13 修回日期:2016-02-03 出版日期:2016-12-25
    • 作者简介:
    • 闫爱斌,男,1983年生于吉林白城,2015年获得合肥工业大学计算机应用技术专业工学博士学位,现为安徽大学计算机科学与技术学院讲师.E-mail:abyan@mail.ustc.edu.cn;梁华国,男,1959年生于安徽合肥,2003年博士毕业于德国斯图加特大学,现为合肥工业大学电子科学与应用物理学院和计算机与信息学院教授、博士生导师.E-mail:huagulg@hfut.edu.cn;黄正峰,男,1978年生于安徽无为,现为合肥工业大学电子科学与应用物理学院副教授、硕士生导师.研究兴趣主要包括星载系统芯片SoC的抗辐射加固、嵌入式系统的综合与测试、数字系统设计自动化等.E-mail:huangzhengfeng@139.com;易茂祥,男,1964年生于安徽广德县,2010年获得合肥工业大学计算机应用技术专业工学博士学位.E-mail:mxyi126@126.com;蒋翠云,女,1962年生于安徽蚌埠,合肥工业大学副教授,主要研究方向为数值分析、有理逼近、容错计算、内建自测试等.E-mail:hgdyun@foxmail.com
    • 基金资助:
    • 国家自然科学基金 (No.61371025,No.61574052,No.61674048,No.61604001)

A Latching-Window Masking Model Considering Overlapped Transient Pulses in Multi-cycle

YAN Ai-bin1,2, LIANG Hua-guo3, HUANG Zheng-feng3, JIANG Cui-yun4, YI Mao-xiang3   

  1. 1. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;
    2. School of Computer Science and Technology, Anhui University, Hefei, Anhui 230009, China;
    3. School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei, Anhui 230009, China;
    4. School of Mathematics, Hefei University of Technology, Hefei, Anhui 230009, China
  • Received:2015-01-13 Revised:2016-02-03 Online:2016-12-25 Published:2016-12-25
    • Supported by:
    • National Natural Science Foundation of China (No.61371025, No.61574052, No.61674048, No.61604001)

摘要:

集成电路工艺水平的提升,使得由单粒子瞬态脉冲造成的芯片失效越发不容忽视.为了准确计算单粒子瞬态脉冲对锁存器造成的失效率,提出一种考虑多时钟周期瞬态脉冲叠加的锁存窗屏蔽模型.使用提出的考虑扇出重汇聚的敏化路径逼近搜索算法查找门节点到达锁存器的敏化路径,并记录路径延迟;在扇出重汇聚路径上,使用提出的脉冲叠加计算方法对脉冲进行叠加;对传播到达锁存器的脉冲使用提出的锁存窗屏蔽模型进行失效率的计算.文中的锁存窗屏蔽模型可以准确计算扇出重汇聚导致的脉冲叠加,并对多时钟周期情形具有很好的适用性.针对ISCAS’85基准电路的软错误率评估结果表明,与不考虑多时钟周期瞬态脉冲叠加的方法相比,文中方法使用不到2倍的时间开销,平均提高7.5%的软错误率评估准确度.

关键词: 锁存窗屏蔽, 脉冲叠加, 多时钟周期, 扇出重汇聚

Abstract:

Technology scaling results in that chip failure caused by single event transient pulses is becoming more and more serious.In order to accurately compute the failure rates introduced by the transient pulses impacting on latches,a novel latching-window masking model considering overlapped transient pulses in multi-cycle is proposed.Firstly,sensitized paths and delays are calculated by the proposed re-convergence aware sensitized path searching algorithm.Further,on re-convergence paths,pulses are overlapped by the proposed pulse overlapping calculation technique.Finally,as regards transient pulses arriving at latches,failure rates are computed by the proposed latching-window masking model.The proposed technique can accurately compute re-convergence induced pulse overlap and it is suitable to estimate failure rates considering multi-cycle.Experimental results for ISCAS'85 benchmarks show that,compared with the approach which has not considered pulse overlap in multi-cycle,the proposed technique improves 7.5% soft error rate accuracy on average with only less than twice the simulation time overhead.

Key words: latching-window masking, pulse overlap, multi-cycle, re-convergence

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