[1] XIANG D,Chakrabarty K,Fujiwara H.Multicast-based testing and thermal-aware test scheduling for 3D ICswith a stacked network-on-chip[J].IEEE Transactions on Computers,2015,(99):1.
[2] Radfar F,Zabihi M,Sarvari R.Comparison between optimal interconnection network in different 2D and 3D noC structures[A].27th IEEE International System-on-Chip Conference (SOCC)[C].Las Vegas,NV:IEEE,2014.171-176.
[3] Elmiligia H,Gebalib F,El-Kharashi W M.Power-aware mapping for 3D-NoC designs using geneticalgorithms[J].Procedia Computer Science,2014,34:538-543.
[4] EghbalA,YaghiniP M,YazdiS S,BagherzadehN.TSV-to-TSV inductive coupling-aware codingscheme for 3D network-on-chip[A].IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)[C].Amsterdam:IEEE,2014.92-97.
[5] Sepulveda J,Gogniat G,Florez D,Diguet J-P,Pires R,Strum M.TSV protection:towards secure 3D-MPSoC[A].IEEE 6th Latin American Symposium onCircuits & Systems (LASCAS)[C].Montevideo:IEEE,2015.1-4.
[6] Ren Y,Liu L,Yin S,Wu Q-H,et al.A vlsi architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration[A].International Symposium on Circuits and Systems[C].Beijing:IEEE,2013.1793-1796.
[7] Radetzki M,Feng C C,Zhao X,Jantsch A.Methods for fault tolerance in networks-on-chip[J].ACM Computing Surveys,2013,46(1):1-38.
[8] Hernandez C,Roca A,Flich J,et al.Fault-tolerant vertical link design for effective 3D stacking[J].IEEE Computer Architecture Letters,2011,10(2):41-44.
[9] OSADA T,GODWIN M.International technology roadmap for semiconductors[EB/OL].http://www.itrs.net/.1999-07-08/1999-07-09.
[10] Ye H,Chi M,Huang S H.A design partitioning algorithm for 3-D integrated circuits[A].IEEE Int.Symp.ComputCommunControl Autom[C].Tainan:IEEE,2010.229-232.
[11] Hsu M K,Balabanov V,Chang Y W.TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2013,32(4):497-509.
[12] Loi I,Mitra S,Lee T H,Fujita S.Benini L.A low-overhead fault tolerance scheme for TSV-based 3D network on chip links[A].International Conference on Computer-Aided Design[C].San Jose:IEEE,2008.598-602.
[13] Patti R.Impact of wafer-level 3D stacking on the yield of ICs[DB/OL].Future Lab.Int.,2007-09-07.
[14] Jiang L,Xu Q,Eklow B.On effective through-silicon via repair for 3-D-stacked ICs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2013,32(4):559-571.
[15] 向东,陈爱,孙家广.基于局部故障块的3维mesh/torus网的容错路由[J].计算机学报,2004,27(5):611-618. Xiang Dong,Chen Ai,Sun Jia-guang.Fault-tolerant routing in 3D meshes/tori based on locally formed fault blocks[J].Chinese Journal of Computers,2004,27(5):611-618.(in Chinese).
[16] 虞潇,李丽,张宇昂,潘红兵,王佳文,韩平.一种面向功耗免死锁三维全动态3D NoC路由算法[J].电子学报,2013,41(2):329-334. Yu Xiao,Li L,Zhang Yu-ang,Pan Hong-bing,Wang Jia-wen,Han Ping.A power-aware dead lock avoid three-dimensionalfull-adaptive routing algorithm for 3D NoC[J].Acta Electronica Sinica,2013,41(2):329-334.(in Chinese)
[17] 张士鉴,韩国栋,沈剑良,柯璘.基于故障链路缓存再利用的NoC容错路由算法[J].计算机辅助设计与图形学学报,2014,26(1):131-137. Zhang Shi-jian,Han Guo-dong,Shen Jian-liang,KeLing.Fault-tolerant routing algorithm of NoC based on buffer reuse of faulty links[J].Journal of Computer-aided Design & Computer Graphics,2014,26(1):131-137.(in Chinese)
[18] 王宇飞,李光顺,吴俊华.无虚拟通道的3D NoC Zone Defense容错路由算法[J].计算机应用研究,2016,33(1):205-209. Wang Yu-fei,Li Guang-shun,Wu Jun-hua.3D NoC zone defense fault-tolerant routing algorithm without virtual channels[J].Application Research of Computers,2016,33(1):205-209.(in Chinese)
[19] 欧阳一鸣,陈义军,梁华国,易茂祥,李建华.一种故障通道隔离的低开销容错路由器设计[J].电子学报,2014,42(11):2142-2149. Ouyang Yi-ming,Chen Yi-jun,Liang Hua-guo,Yi Mao-xiang,Li Jian-hua.Design of a low-overhead fault channel isolated fault-tolerant router[J].Acta Electronica Sinica,2014,42(11):2142-2149.(in Chinese)
[20] 冯超超,张民选,李晋文,戴艺.一种可配置双向链路的片上网络容错偏转路由器[J].计算机研究与发展,2014,51(2):454-463. Feng Chao-chao,Zhang Ming-xuan,Li Jin-wen,Dai Yi.A fault-tolerant deflection router with reconfigurable bidirectional link for NoC[J].Journal of Computer Research and Development,2014,51(2):454-463.(in Chinese)
[21] Lei Zhou,Ning Wu,Fen Ge.3-D spidergon:3-D topology of delay optimization for networks-on-chip[J].Transactions of Nanjing University of Aeronautics & Astronautics,2011,28(4):372-378.
[22] Akbari S,Shafieey A,Fathy M,Berangi R.AFRA:A low cost high performance reliable routing for 3d mesh NoCs[A].Design,Automation & Test in Europe Conference & Exhibition[C].Dresden:IEEE,2012.332-337.
[23] Ahmed A B,et al.Graceful deadlock-free fault-tolerant routing algorithm for 3D network-on-chip architecture[J].Elsevier Journal of Parallel and Distributed Computing,2014,74(4):2229-2240.
[24] Jouybari H N,Mohammadi K.A low overhead,fault tolerant and congestion aware routing algorithmfor 3D mesh-based network-on-chips[J].Microprocessors and Microsystems,2014,38(8):991-999.
[25] Rahmani A M,Vaddina K R,Atifk L,Liljeberg P,Losilaj P,Enhunenh T.High-performance and fault-tolerant 3D NoC-bus hybrid architecture using ARB-NET based adaptive monitoring platform[J].IEEE Transactions on Computers,2014,61(3):734-747.
[26] Hsieh A C,Hwang T T,Chang M T.TSV redundancy:architecture and design issues in 3D IC[A].Design,Automation & Test in Europe Conference & Exhibition[C].Dresden:IEEE,2010.166-171.
[27] Ditomaso D,Kodi A,Louri A.QORE:A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers[A].IEEE 20th International Symposium High Performance Computer Architecture (HPCA)[C].Orlando,FL:IEEE,2014.320-331.
[28] Deorio A,Fick D,et al.A reliable routing architecture and algorithm for NoCs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and System,2012,31(5):726-739.
[29] Pullini A,Angiolini F,Murali S.et al.Bringing NoCs to 65 nm[J].IEEE Micro,2007,27(5):75-85.
[30] Passas G,Katevenis M,Pnevmatikatos D.Crossbar NoCsare scalable beyond 100 nodes[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and System,2012,31(4):573-585.
[31] Neishaburi M H,Zilic Z.Reliability aware NoC router architecture using input channel buffer sharing[A].Great Lake Symposium on VLSI[C].New York:ACM,2009.511-516.
[32] 欧阳一鸣,张一栋,梁华国,黄正峰.三维片上网络故障及拥塞感知的容错路由器设计[J].电子学报,2013.41(5):912-917. Ouyang Yi-ming,Zhang Yi-dong,Liang Hua-guo,Huang Zheng-feng.A fault-tolerant design of faults and congestion-aware router in three-dimensional network-on-chip[J].Acta Electronica Sinica,,2013.41(5):912-917.(in Chinese)
[33] LATIF K,et al.A novel topology-independent router architecture to enhance reliability and performance of networks-on-chip[A].IEEE IntSymp on Defect and Fault Tolerance in VLSI and Nanotechnology Systems[C].Vancouver:IEEE,2011.454-462.
[34] Latif K,Rahmani A M,Liang G,et al.PVS-NoC:partial virtual channel sharing NoC architecture[A].International Euromicro Conference[C].New York:IEEE,2011.470-477.
[35] Zhang Y,Morris J,Kodi A.Design of a performance enhanced and power reduced dual-crossbar network-on-chip (NoC) architecture[J].Microprocessors and Microsystems,2011,35(2):110-118.
[36] Ghiribaldi A,Strano A,Favalli M,et al.Power efficiency of switch architecture extensions for fault tolerant NoC design[A].International Green Computing Conference[C].San Jose:IEEE,2012.1-6.
[37] Garrou P,Bower C,Ramm P.Handbook of 3D Integration:Technology and Application of 3D Integrated Circuits(1-2)[M].Weinheim:WILEY-VCH Verlag GmbH & Co.KGaA,2008.
[38] Miyakawa N,et al.A 3D prototyping chip based on a wafer-level stacking technology[A].Asia and South Pacific Design Automation Conference[C].Yokohama:IEEE,2009.416-420.
[39] Swinnen B,Ruythooren W,Moor P D,et al.3D integration by cu-cuthermo-compression bonding of extremely thinned bulk-Si die containing 10μm pitch Through-Si Vias[A].International Electron Devices Meeting[C].San Francisco:IEEE,2006.1-4.
[40] A Topol,La Tulipe D C,Shi L,S Alam M,et al.Enabling SOI based assembly technology for three-dimensional integrated circuits[A].International Electron Devices Meeting[C].San Francisco:IEEE,2005.352-355.
[41] Kim D H,Athikulwongse K,Lim S K.Study of through-silicon-via impact on the 3-D stacked IC Layout[J].IEEE Transactions on VLSI Systems,2013,21(5):862-874.
[42] H Ying,A Jaiswal,T Hollstein.Deadlock-free generic routing algorithms for 3-Dimensional networks-on-chip with reduced vertical link density topologies[J].Journal of Systems Architecture,2013,59(7):528-542.
[43] Bahmani M,Sheibanyrad A,Pétrot F,et al.A 3D-NoC router implementation exploiting vertically-partially-connected topologies[A].IEEE Computer Society Annual Symposium on VLSI[C].Los Alamitos:IEEE Computer Society,2012.9-14.
[44] Dubois F,Sheibanyrad A,Pétrot F,et al.Elevator-first:a deadlock-free distributed routing algorithm for vertically partially connected 3D-NoCs[J].IEEE Transactions on Computers,2011,62(3):609-615.
[45] Pasca V,Anghel L,Benabdenbi M.Error resilience exploration in 3D systems[A].IEEE International On-Line Testing Symposium[C].Chania:IEEE,2013.1-5.
[46] Kang U,Chung H J.8 Gb 3-D DDR3 DRAM using through-silicon-via technology[J].IEEE Journal of Solid-State Circuits,2010,41(1):111-119.
[47] Zhang J,Yu L,Yang H.Self-test method and recovery mechanism for high frequency TSV array[A].IEEE/IFIP International Conference on VLSI and System-on-Chip[C].Hong Kong:IEEE,2011.260-265.
[48] Pasca V,Anghel L,Rusu C,Locatelli R,Coppola M.Error resilience of intra-die and inter-die communication with 3d spidergon STNoC[A].Design,Autumation& Test in Europe Conference[C].Dresden:IEEE,2010.275-278.
[49] Pasricha S,et al.A framework for TSV serialization-aware synthesis of application specific 3D Networks-on-Chip[A].International Conference on VLSI Design[C].Hyderabad:IEEE,2012.268-273.
[50] Miller F,Wild T,Herkersdorf A.Virtualized and fault-tolerant inter-layer-links for 3D-ICs[J].Microprocessors and Microsystems,2013,37(8):823-835.
[51] Liu C,Zhang L,Han Y,Li X W.Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip[A].Asia and South Pacific Design Automation Conference[C].Yokohama:IEEE,2011.357-362. |