VLSI电路中互连线的延迟及串扰的数值模拟
阮刚;肖夏;宋任儒;ReinhardStreiter;ThomasOtto;ThomasGessner
Numerical Simulation of Time Delay and Cross-talk Noise for the Interconnect in VLSI Circuits
RUAN Gang;XIAO Xia;SONG Ren-ru;Reinhard Streiter;Thomas Otto;Thomas Gessner
电子学报
.
2000, (5): 142
-144
.
