Construction of Optimum Circuit for AES S-Box Based on an Enhanced Delay-Aware Common Subexpression Elimination Algorithm

DAI Qiang, DAI Zi-bin, LI Wei

ACTA ELECTRONICA SINICA ›› 2019, Vol. 47 ›› Issue (1) : 129-136.

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ACTA ELECTRONICA SINICA ›› 2019, Vol. 47 ›› Issue (1) : 129-136. DOI: 10.3969/j.issn.0372-2112.2019.01.017

Construction of Optimum Circuit for AES S-Box Based on an Enhanced Delay-Aware Common Subexpression Elimination Algorithm

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2019, 47(1): 129-136. https://doi.org/10.3969/j.issn.0372-2112.2019.01.017

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