With the feature size of VLSI scaling down

interconnection delays begin to dominate the circuit performance.Interconnect nets reduction become an important part of high level synthesis.We present an algorithm which cope allocation and floorplan problems simultaneously

we use Min-cut method to multi-partition scheduled DFG

implementing resource allocation as well as mapping the partition procedure to Slicing structure based floorplan.During the partition procedure

floorplan informations are used to direct allocation

thus interconnections are efficiently optimized.Design examples are presented to help concluding that our algorithm is very efficient.