浙江大学信息科学与工程学院信息与电子工程学系,浙江,杭州,310027
纸质出版:2002
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陈 英, 朱大中. 可编程SAW滤波器CMOS集成电路的研究[J]. 电子学报, 2002,30(8):1207-1209.
CHEN Ying, ZHU Da-zhong. The Research of Programmable SAW Filter CMOS IC[J]. Acta Electronica Sinica, 2002, 30(8): 1207-1209.
本文介绍了一种采用1 μm CMOS工艺实现的可编程声表面波滤波器的八位取样、加权、控制、叠加集成电路
并对电路的性能进行了模拟和测试
同时与延迟线型、多组IDT型的声表面波滤波器以多芯片模式进行在线功能测试.该电路由两个三明治电容和两个高宽长比的高跨导NMOS晶体管组成.该电路结构简单
制造工艺与传统的CMOS工艺兼容.该集成电路的工作频率范围为15MHz~250MHz时
插入损耗为-8dB~-20dB
加权电路开关比(on/off ratio)为7dB~18dB左右.
A 1μm CMOS eight-bit integrated circuit was designed and fabricated
used for sampling
weighting
controlling and summing of both SAW delay lines and SAW IDTs in multi-chip module (MCM) programmable SAW filter.Its characteristics and performances are simulated and tested.The circuit of each bit consists of two sampling capacitances which are made in sandwich structure of two layers of Al and one layer of poly-silicon and also consists of two high transconductance N-MOSFETs with high W/L ratio.The circuit is simple and compatible with traditional CMOS processes.Its insertion loss is about -8dB~-20dB within 15MHz~250MHz frequency and the weighted circuit's on/off ratio is within the range from 7dB to 18dB.
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