KE Dao-ming, CHEN Jun-ning, ZHUO Guo-xiang, et al. The Analysis of Latch Up Characteristics in High Temperature CMOSIntegrated Circuits[J]. Acta Electronica Sinica, 2002, 30(12): 1894-1896.
KE Dao-ming, CHEN Jun-ning, ZHUO Guo-xiang, et al. The Analysis of Latch Up Characteristics in High Temperature CMOSIntegrated Circuits[J]. Acta Electronica Sinica, 2002, 30(12): 1894-1896.DOI：
The paper has analyzed Latch-up characteristics in high temperature CMOS integrated circuits.In this paper
we propose a latch-up effect model for submicron and deep submicron integrated circuits.We find there are two sub-models about CMOS integrated circuit Latch-up effect.The base width of a parasitic transistor is long in a big size MOS IC
and the base transport factor dominates.The device size is small in VLSI and ULSI.The base width of a parasitic transistor is shorter
and emission efficiency dominates.But their holding currents are all negative index number power about temperatures.The paper has given relations between holding current and temperatures from 25℃ to 300℃ range.The experiment results are essential agreement with the model that the paper has given.
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