A robust configurable multiplexing approach is proposed

which presented 2∶1

3∶1

4∶1

5∶1 multiplex modes.Its cascade structure can realize all multiplexing modes except prime numbers of greater than 6.Based on this approach

an IC was designed to achieve the 10:1 multiplexing at the bit rate of 1.25Gbps.It used high speed units to improve the design efficiency and to realize low power.It has been developed using 0.35μm CMOS technology and the layout was finished in full custom method.The chip was realized through a foundry technology and measured on wafer.The chip area is 24.19 mm

2

.The power dissipation is 174.84mW under a 3.3V supply.The measured output voltage is 2.42V

p-p

based on 50Ω load

the d

uty cycle is 49% and the phase jitter is 35ps rms at the 1.25Gbps standard bit rate.The highest speed of serial data is 1.62Gbps.