With the popularization of embedded systems

low power design has become one of the most challenging tasks in the embedded system development.This paper presents a novel two-level power estimation model operating at the system-level

which including a microarchitecture level model to support hardware optimization and an instruction level model to support software compiling optimization.The microarchitecture level model based upon the information of components structure.The instruction level model based upon the microarchitecture model.Thus the proposed methodology provides an accurate and rapid model to evaluate embedded system high level design.