A self-tuning

adaptive 1.9GHz fractional-N/integer PLL based frequency synthesizer is proposed in the paper.A combined tuning technique of digital tuning and analog tuning is used to improve the phase noise of frequency synthesizer by decreasing the gain of VCO.The adaptive loop is introduced for automatic adjustment of the loop bandwidth

which can quicken the locking process.Two operation modes (integer/fractional-N) are achieved by switching on/off the output signal of ΣΔ modulator.Just a programmable counter is needed for the swallow pulse divider.The on-chip VCO achieves a low phase noise by utilizing a bias filter technique and a differential inductor

and a 1.7GHz~2.1GHz tuning range by a switched capacitor array.Based on 0.18 μ m 1.8V SMIC CMOS technology

SpectreVerilog simulation shows that the frequency synthesizer has a 100 kHz loop bandwidth

a＜15 μ s settling time

and the phase noise is lower than -123dBc at 600kHz offset.