The leakage power issue is challenging high-performance microprocessor design

especially as feature size shrinks.Not only are low leakage technologies and circuits well researched

but also architectural control methods are studied hotly.Caches represent a sizable fraction of the total power consumption

so they need to be managed firstly.LRU is the most popular replacement algorithm used in set associative caches

but researches show that the latter blocks in LRU list are rarely accessed again.LRU-assist algorithm proposed in this paper exploits existing LRU information to expand the low leak portion in cache in addition to the time-based drowsy and decay mechanism.Simulation results show that the cache off ratio can be increased by 15% and leakage power is greatly saved with negligible performance overhead.