A new adiabatic logic circuit adopting two-phase non-overlap power clocks-Clocked Transmission Gate Adiabatic Logic circuit was designed by using the bootstrap effect of NMOS transistors

so that it could charge or discharge output loads in a fully adiabatic manner.Based on this circuit

a novel adiabatic SRAM was designed.So it could recover the charge of large switching capacitances on word-lines

write bit-lines

sense amplified lines and address decoders in a fully adiabatic manner.Using the parameters of TSMC 0.25 μ m CMOS device

the adiabatic SRAM designed was simulated by HSPICE.The simulation results indicate that this SRAM has correct logic function and the character of clearly low power.