It's crucial to optimize global interconnect performance in ultra deep sub-micron System-On-a-Chip designs.In this paper

the optimized method to improve delay-bandwidth performance under crosstalk constraint

suitable to various technology nodes

is proposed from analytical formula based on distributed RLC model.It's verified through HSPICE simulation that

by utilizing this method

the optimization of edge-length global interconnect of mainstream 90 nm technology can achieve delay of 182 ps

data bandwidth of 1.43GHz/ μ m

and near line peak crosstalk voltage within 0.096

V

dd

.Through cross-section parameters and performance targets determined by this method under various technology nodes

the trend of global interconnect design is reasonably predicted along with continuously sca

ling down of semiconductor devices.