一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

徐叶; 张培勇; 李豪; 黄开天

doi:10.12263/DZXB.20201137

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一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

学术论文 | 更新时间：2025-12-08

- 一种具有自适应优化电源抑制比的低静态电流无片外电容LDO
- A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique
- 电子学报 2022年50卷第7期页码：1674-1683
- 作者机构：
  
  1.浙江大学超大规模集成电路研究所，浙江杭州 310027
  2.南方电网科学研究院有限责任公司信息安全中心，广东广州 510663
- 作者简介：
  
  [ "徐叶女，1995年生，浙江江山人.浙江大学信息与电子工程学院硕士研究生.主要研究方向为模拟集成电路.E-mail: yeahz@zju.edu.cn" ]
  [ "张培勇（通讯作者）男，1977年生，安徽安庆人.浙江大学获博士.主要研究方向为超大规模集成电路设计.E-mail: zhangpy@zju.edu.cn" ]
  [ "李豪男，1995年生，浙江嘉兴人.浙江大学信息与电子工程学院博士研究生.主要研究方向为SoC电路设计.E-mail: 11931078@zju.edu.cn" ]
  [ "黄开天男，1992年生，广西钦州人.清华大学硕士.主要研究方向为电力物联网通信与传感器应用安全、密码芯片应用.E-mail: huangkt@csg.cn" ]
- 基金信息：
  
  国家重点研发计划(2018YFB0904900;2018YFB0904902)
- DOI：10.12263/DZXB.20201137
  中图分类号： TN431.1;
- 收稿：2020-10-14，
  
  修回：2021-02-19，
  
  纸质出版：2022-07-25
- 稿件说明：
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徐叶,张培勇,李豪等.一种具有自适应优化电源抑制比的低静态电流无片外电容LDO[J].电子学报,2022,50(07):1674-1683.

XU Ye,ZHANG Pei-yong,LI Hao,et al.A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique[J].ACTA ELECTRONICA SINICA,2022,50(07):1674-1683.
徐叶,张培勇,李豪等.一种具有自适应优化电源抑制比的低静态电流无片外电容LDO[J].电子学报,2022,50(07):1674-1683. DOI： 10.12263/DZXB.20201137.

XU Ye,ZHANG Pei-yong,LI Hao,et al.A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique[J].ACTA ELECTRONICA SINICA,2022,50(07):1674-1683. DOI： 10.12263/DZXB.20201137.

摘要

为改善无片外电容LDO（Capacitor-Less Low-DropOut regulator，CL-LDO）的电源抑制比（Power Supply Rejection，PSR），本文提出一种低静态电流PSR自适应优化方案.采用push-pull放大器，避免复杂的频率补偿电路与片外大电容，缩小了面积.为优化中频段PSR，在功率管栅极注入一个与频率相关的补偿电流.采用低静态电流的补偿电流动态调整方案，减小压差和负载电流变化对PSR优化效果的影响.该LDO基于0.11 μm CMOS工艺，芯片面积为0.026 mm

.测试结果表明，在0.1~80 mA负载电流下，静态电流最大值为55

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1.69333339

2.96333337

A.在8 kHz到1 MHz频率范围内，在不同压差和负载电流下，PSR最大优化值为21~37 dB.

Abstract

To improve the power supply rejection ratio(PSR) of capacitor-less low dropout regulator(CL-LDO)

this paper proposes an adaptive optimization technique for PSR with low quiescent current. Using push-pull amplifier avoids complex frequency compensation circuits and a bulky external capacitor

thereby reducing the area. To optimize the mid-band PSR

a frequency-dependent compensation current is injected into the gate of the pass transistor. Moreover

a low power dynamic adjustment scheme of the compensation current is adopted to alleviate the impacts of the dropout voltage and load current variations on the optimal PSR improvement. This LDO was designed and fabricated in a 0.11 μm CMOS technology with an active area of 0.026 mm

. The experimental results show that the maximum quiescent current is 55 μA with 0.1-80 mA load current. In the frequency range of 8 kHz to 1 MHz

the maximum PSR improvement is 21-37 dB with different dropout voltages and load currents.

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references

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