基于机器学习的高效率集成电路DFT技术研究

蔡志匡; 赵泽宇; 杨涵; 王子轩; 郭宇锋

doi:10.12263/DZXB.20220858

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基于机器学习的高效率集成电路DFT技术研究

学术论文 | 更新时间：2025-12-11

- 基于机器学习的高效率集成电路DFT技术研究
- Research on High-Efficiency Integrated Circuit DFT Technology Based on Machine Learning
- 电子学报 2023年51卷第12期页码：3473-3482
- 作者机构：
  
  1.南京邮电大学集成电路科学与工程学院,江苏南京 210023
  2.南京邮电大学射频集成与微组装技术国家地方联合工程实验室,江苏南京 210023
- 作者简介：
  
  [ "蔡志匡男，1983年7月出生于江苏连云港.2014年毕业于东南大学电子科学与工程学院.现任南京邮电大学集成电路科学与工程学院教授、博士生导师.主要研究方向为低功耗集成电路设计与测试. E-mail: whczk@njupt.edu.cn" ]
  [ "赵泽宇男，1999年3月出生于江苏徐州.2021年进入南京邮电大学集成电路科学与工程学院，在读硕士研究生.主要研究方向为可测性设计、机器学习. E-mail: 1021021028@njupt.edu.cn" ]
  [ "杨涵女，1997年7月出生于云南昭通.2019年进入南京邮电大学电子与光学工程学院、微电子学院，硕士研究生已毕业.主要研究方向为可测性设计、机器学习. E-mail: 1319025322@njupt.edu.cn" ]
  [ "王子轩（通讯作者）男，1982年11月出生于江苏徐州.2014年毕业于东南大学电子科学与工程学院.现任南京邮电大学集成电路科学与工程学院副教授，硕士生导师.主要研究方向为高能效集成电路设计. E-mail: wangzixuan@njupt.edu.cn" ]
  [ "郭宇锋男，1974年5月出生于河南洛阳，2005年毕业于电子科技大学，获微电子学博士学位.现任南京邮电大学集成电路科学与工程学院教授、博士生导师.主要研究方向为新型微电子器件、集成电路设计、无线能量和信息协同传输. E-mail: yfguo@njupt.edu.cn" ]
- 基金信息：
  
  国家重点研发计划项目(2018YFB2202005);国家自然科学基金(61974073;U22B2024)
- DOI：10.12263/DZXB.20220858
  中图分类号： TN47;TP181
- 收稿：2022-07-20，
  
  修回：2022-11-01，
  
  纸质出版：2023-12-25
- 稿件说明：
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蔡志匡,赵泽宇,杨涵等.基于机器学习的高效率集成电路DFT技术研究[J].电子学报,2023,51(12):3473-3482.

CAI Zhi-kuang,ZHAO Ze-yu,YANG Han,et al.Research on High-Efficiency Integrated Circuit DFT Technology Based on Machine Learning[J].ACTA ELECTRONICA SINICA,2023,51(12):3473-3482.
蔡志匡,赵泽宇,杨涵等.基于机器学习的高效率集成电路DFT技术研究[J].电子学报,2023,51(12):3473-3482. DOI： 10.12263/DZXB.20220858.

CAI Zhi-kuang,ZHAO Ze-yu,YANG Han,et al.Research on High-Efficiency Integrated Circuit DFT Technology Based on Machine Learning[J].ACTA ELECTRONICA SINICA,2023,51(12):3473-3482. DOI： 10.12263/DZXB.20220858.

摘要

本文提出了一种基于机器学习的高效率集成电路可测性设计技术.该技术以自动收集的数据作为训练集，以决定系数为评价指标，为每类目标参数选择出最佳预测模型，并预测出基于不同配置参数的可测性设计结构所对应的目标参数，最后使用最优配置推断技术，以目标参数差值的加权和作为衡量指标，输出最优的可测性设计配置参数.实验数据表明，针对可测性设计技术中最重要的测试覆盖率参数，平均预测误差仅为0.075 6%；根据目标参数差值的加权和的最小值情况，实现高效推断芯片可测性设计的最优配置参数.该技术的预测效果具有高可靠性，能够在保证高测试覆盖率的前提下，有效减少测试成本和面积开销等.

Abstract

This paper proposes a high-efficiency design for test (DFT)technique for integrated circuits based on machine learning. The technology uses the automatically collected data as the training set and determination coefficient as the evaluation index

selects the best prediction model for each type of target parameters

and predicts the target parameters corresponding to the design for test structure based on different configuration parameters

and finally uses the optimal configuration. The inference technology uses the weighted sum of difference value of target parameters as a measure to output the optimal design for test configuration parameters. The experimental data shows that for the most important test coverage parameter in design for test technology

the average prediction error is only 0.075 6%; according to the minimum value of weighted sum of difference value of target parameters

the optimal configuration parameters of the design for test can be efficiently inferred. The prediction effect of this technology has high reliability

and can effectively reduce the test cost and area overhead on the premise of ensuring high test coverage.

关键词

Keywords

references

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